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參數(shù)資料
| 型號(hào)： | 74AHC138 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 3-to-8 line decoder/demultiplexer; inverting |
| 中文描述： | 3至8線路解碼器/解復(fù)用器;反相 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 84K |
| 代理商： | 74AHC138 |
1999 Sep 27
2
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
74AHC138;
74AHCT138
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger
actions
Multiple input enable for easy
expansion
Ideal for memory chip select
decoding
Inputs accept voltages higher than
V
CC
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Specified from
40 to +85 and +125
°
C.
DESCRIPTION
The 74AHC/AHCT138 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT138 decoders accept three binary weighted address inputs
(A
0
, A
1
and A
2
) and when enabled, provide 8 mutually exclusive active LOW
outputs (Y
0
to Y
7
).
The ‘138’ features three enable inputs: two active LOW (E
1
and E
2
) and one
active HIGH (E
3
). Every output will be HIGH unless E
1
and E
2
are LOW and E
3
is HIGH.
This multiple enable function allows easy parallel expansion of the ‘138’ to a
1-of-32 (5 to 32 lines) decoder with just four ‘138’ ICs and one inverter.
The ‘138’ can be used as an eight output demultiplexer by using one of the
active LOW enable inputs as the data input and the remaining enable inputs as
strobes. Unused enable inputs must be permanently tied to their appropriate
active HIGH or LOW state.
The ‘138’ is identical to the ‘238’ but has inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay A
n
to Y
n
propagation delay E
3
to Y
n
; E
n
to Y
n
input capacitance
output capacitance
power dissipation capacitance
C
L
= 15 pF; V
CC
= 5 V
C
L
= 15 pF; V
CC
= 5 V
V
I
= V
CC
or GND
4.4
4.2
3.0
4.0
18
4.4
4.3
3.0
4.0
23
ns
ns
pF
pF
pF
C
I
C
O
C
PD
C
L
= 50 pF; f = 1 MHz;
notes 1 and 2
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