參數(shù)資料
型號： 74AHC241PW,118
廠商： NXP Semiconductors
文件頁數(shù)： 13/15頁
文件大?。?/td> 0K
描述： IC BUFFER/LINEDVR 3ST TSSOP20
標準包裝： 1
系列： 74AHC
邏輯類型： 緩沖器/線路驅(qū)動器，非反相
元件數(shù)： 2
每個元件的位元數(shù)： 4
輸出電流高，低： 8mA，8mA
電源電壓： 2 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 標準包裝
其它名稱： 568-5240-6
74AHC_AHCT241_1
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 11 January 2010
7 of 15
NXP Semiconductors
74AHC241; 74AHCT241
Octal buffer/line driver; 3-state
[1]
Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2]
tpd is the same as tPLH and tPHL; ten is the same as tPZH and tPZL; tdis is the same as tPLZ and tPHZ.
[3]
CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(C
L × VCC
2
× f
o) = sum of outputs.
11. Waveforms
ten
enable time
1OE to 1Yn; see Figure 6
VCC = 4.5 V to 5.5 V; CL = 15 pF
-
3.7
6.6
1.0
7.8
9.2
ns
VCC = 4.5 V to 5.5 V; CL = 50 pF
-
5.4
9.5
1.0
11.1
12.4
ns
2OE to 2Yn; see Figure 7
VCC = 4.5 V to 5.5 V; CL = 15 pF
-
3.7
6.6
1.0
7.8
9.2
ns
VCC = 4.5 V to 5.5 V; CL = 50 pF
-
5.4
9.5
1.0
11.1
12.4
ns
tdis
disable time
1OE to 1Yn; see Figure 6
VCC = 4.5 V to 5.5 V; CL = 15 pF
-
4.8
7.8
1.0
8.8
9.7
ns
VCC = 4.5 V to 5.5 V; CL = 50 pF
-
7.1
10.5
1.0
11.4
13.5
ns
2OE to 2Yn; see Figure 7
VCC = 4.5 V to 5.5 V; CL = 15 pF
-
4.8
7.8
1.0
8.8
9.7
ns
VCC = 4.5 V to 5.5 V; CL = 50 pF
-
7.1
10.5
1.0
11.4
13.5
ns
CPD
power
dissipation
capacitance
VI = GND to VCC; CL = 50 pF;
fi = 1 MHz
-
9
-
pF
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
Conditions
25
°C
40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
(85
°C)
Max
(125
°C)
Measurement points are given in Table 8.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 5.
Propagation delay input (nAn) to output (nYn)
mgu781
nAn input
nYn output
tPHL
tPLH
GND
VI
VM
VOH
VOL
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