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參數(shù)資料
| 型號： | 74AHC377 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal D-type flip-flop with data enable; positive-edge trigger |
| 中文描述： | 八路D型觸發(fā)器數(shù)據(jù)使觸發(fā)器，積極邊緣觸發(fā) |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 101K |
| 代理商： | 74AHC377 |
2000 Aug 15
2
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
Ideal for addressable register applications
Data enable for address and data synchronization
Eight positive-edge triggered D-type flip-flops
See “273” for master reset version
See “373” for transparent latch version
See “374” for 3-state version
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from
40 to +85 and from
40 to +125
°
C.
DESCRIPTION
The 74AHC/AHCT377 D-type flip-flops are high-speed
silicon-gate CMOS devices and are pin compatible with
low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT377 devices have eight edge-triggered,
D-type flip-flops with individual D inputs and Q outputs.
A common clock (CP) input loads all flip-flops
simultaneously when the data enable (E) is LOW. The
state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Q
n
) of the flip-flop.
TheE input must be stable only one set-up time prior to the
LOW-to-HIGH transition for predictable operation.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay;
CP to Q
n
maximum clock frequency
input capacitance
power dissipation
capacitance
C
L
= 15 pF; V
CC
= 5 V
3.9
4.0
ns
f
max
C
I
C
PD
C
L
= 15 pF; V
CC
= 5 V
V
I
= V
CC
or GND
C
L
= 50 pF; f = 1 MHz;
notes 1 and 2
175
3.0
20
140
3.0
23
MHz
pF
pF
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| 74AHC377_08 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Octal D-type flip-flop with data enable; positive-edge trigger |
| 74AHC377D | 功能描述:觸發(fā)器 OCT D-TYPE EDGE TRIGGER RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74AHC377D,112 | 功能描述:觸發(fā)器 OCT D-TYPE EDGE RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74AHC377D,118 | 功能描述:觸發(fā)器 OCT D-TYPE EDGE RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74AHC377D-Q100J | 功能描述:IC D-TYPE POS TRG SNGL 20SOIC 制造商:nxp semiconductors 系列:汽車級，AEC-Q100，74AHC 包裝:帶卷（TR） 零件狀態(tài):有效 功能:標(biāo)準(zhǔn) 類型:D 型 輸出類型:非反相 元件數(shù):1 每元件位數(shù):8 頻率 - 時(shí)鐘:120MHz 不同 V，最大 CL 時(shí)的最大傳播延遲:10.5ns @ 5V，50pF 觸發(fā)器類型:正邊沿 電流 - 輸出高，低:8mA，8mA 電壓 - 電源:2 V ~ 5.5 V 電流 - 靜態(tài):4μA 輸入電容:3pF 工作溫度:-40°C ~ 125°C（TA） 安裝類型:表面貼裝 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 標(biāo)準(zhǔn)包裝:2,000 |
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