參數(shù)資料
型號(hào)： 74AHC86
廠商： NXP Semiconductors N.V.
英文描述： Quad 2-input EXCLUSIVE-OR gate(四2輸入異或門)
中文描述： 四2輸入異或門（四2輸入異或門）
文件頁(yè)數(shù)： 2/16頁(yè)
文件大小： 75K
代理商： 74AHC86
1999 Sep 17
2
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74AHC86; 74AHCT86
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
Inputsacceptsvoltageshigherthan
V
CC
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Specified from
40 to +85
°
C and
40 to +125
°
C.
DESCRIPTION
The 74AHC/AHCT86 are high-speed
Si-gate CMOS devices and are pin
compatible with Low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
no. 7A.
The 74AHC/AHCT86 provides the
2-input EXCLUSIVE-OR function.
QUICK REFERENCE DATA
Ground = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
FUNCTION TABLE
See note 1.
Note
1.
H = HIGH voltage level;
L = LOW voltage level.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay
nA, nB to nY
input capacitance
output capacitance V
I
= V
CC
or GND
power dissipation
capacitance
C
L
= 15 pF;
V
CC
= 5 V
V
I
= V
CC
or GND
3.4
3.4
ns
C
I
C
O
C
PD
3.0
4.0
10
3.0
4.0
12
pF
pF
pF
C
L
= 50 pF;
f = 1 MHz;
notes 1 and 2
INPUT
OUTPUT
nA
nB
nY
L
L
H
H
L
H
L
H
L
H
H
L
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PACKAGES
PINS
PACKAGE
MATERIAL
CODE
74AHC86D
74AHC86PW
74AHCT86D
74AHCT86PW
74AHC86D
74AHC86PW DH
74AHCT86D
74AHCT86PW DH
14
14
14
14
SO
plastic
plastic
plastic
plastic
SOT108-1
SOT402-1
SOT108-1
SOT402-1
TSSOP
SO
TSSOP
相關(guān)PDF資料
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74AHCT86 Quad 2-input EXCLUSIVE-OR gate(四2輸入異或門)
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