參數(shù)資料
型號(hào): 74AHCT00PWDH
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: Quadruple 2-Input Positive-NAND Gates With Open-Drain Outputs 14-TSSOP -40 to 85
中文描述: AHCT/VHCT SERIES, QUAD 2-INPUT NAND GATE, PDSO14
封裝: PLASTIC, TSSOP-14
文件頁數(shù): 2/16頁
文件大小: 74K
代理商: 74AHCT00PWDH
1999 Sep 23
2
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74AHC00; 74AHCT00
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger
actions
Inputs accept voltages higher than
V
CC
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Specified from
40 to +85 and +125
°
C.
DESCRIPTION
The 74AHC/AHCT00 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL).
They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT00 provides the
2-input NAND function.
FUNCTION TABLE
See note 1.
Note
1.
H = HIGH voltage level;
L = LOW voltage level.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
PINNING
INPUT
OUTPUT
nA
nB
nY
L
L
H
H
L
H
L
H
H
H
H
L
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay
nA, nB to nY
input capacitance
output capacitance
power dissipation
capacitance
C
L
= 15 pF;
V
CC
= 5 V
V
I
= V
CC
or GND
3.2
3.3
ns
C
I
C
O
C
PD
3.0
4.0
7.0
3.0
4.0
7.0
pF
pF
pF
C
L
= 50 pF;
f = 1 MHz;
notes 1 and 2
PIN
SYMBOL
DESCRIPTION
1, 4, 9 and 12
2, 5, 10 and 13
3, 6, 8 and 11
7
14
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
data inputs
data inputs
data outputs
ground (0 V)
DC supply voltage
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