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參數(shù)資料
| 型號： | 74AHCT139PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual 2-to-4 line decoder/demultiplexer |
| 中文描述： | AHCT/VHCT SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, SOT-403-1, TSSOP-16 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 582K |
| 代理商： | 74AHCT139PWDH |
1999 Sep 01
2
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
74AHC139;
74AHCT139
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt trigger actions
Inputs accept voltages higher than V
CC
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from
40 to +85
°
C and
40 to +125
°
C.
DESCRIPTION
The 74AHC/AHCT139 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74AHC/AHCT139 are high-speed, dual 2-to-4 line
decoder/demultiplexers.
This device has two independent decoders, each
accepting two binary weighted inputs (nA
0
and nA
1
) and
providing four mutually exclusive active LOW outputs
(nY
0
to nY
3
). Each decoder has an active LOW enable
input (nE). When nE is HIGH, every output is forced HIGH.
The enable input can be used as the data input for a 1-to-4
demultiplexer application.
The ‘139’ is identical to the HEF4556 of the HE4000B
family.
QUICK REFERENCE DATA
Ground = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay
nA
n
to nY
n
nE to nY
n
input capacitance
output capacitance
power dissipation capacitance
C
L
= 15 pF; V
CC
= 5 V
3.9
3.4
3.0
4.0
25.76
4.7
3.6
3.0
4.0
22.36
ns
ns
pF
pF
pF
C
I
C
O
C
PD
V
I
= V
CC
or GND
C
L
= 50 pF; f = 1 MHz;
notes 1 and 2
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