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參數(shù)資料
| 型號： | 74AHCT273 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Quadruple 2-Input Positive-AND Gates 14-SOIC -40 to 85 |
| 中文描述： | 八路D型觸發(fā)器的復(fù)位觸發(fā)器，積極邊緣觸發(fā) |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 92K |
| 代理商： | 74AHCT273 |
1999 Sep 01
2
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
FEATURES
Ideal buffer for MOS microcontroller or memory
Common clock and master reset
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt trigger actions
Inputs accepts voltages higher than V
CC
See ‘377’ for clock enable version
See ‘373’ for transparent latch version
See ‘374’ for 3-state version
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from
40 to +85
°
C and
40 to +125
°
C.
DESCRIPTION
The 74AHC/AHCT273 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74AHC/AHCT273 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs.
Thecommonclock(CP)andmasterreset(MR)inputsload
and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Q
n
) of the flip-flop.
All outputs will be forced LOW independently of clock or
data inputs by a LOW on the MR input.
The device is useful for applications where the true output
only is required and the clock and master reset are
common to all storage elements.
QUICK REFERENCE DATA
Ground = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay
CP to Q
n
MR to Q
n
maximum clock frequency
input capacitance
output capacitance
power dissipation
capacitance
C
L
= 15 pF; V
CC
= 5 V
4.2
3.7
120
3.0
4.0
14.0
4.0
3.9
120
3.0
4.0
18.0
ns
ns
MHz
pF
pF
pF
f
max
C
I
C
O
C
PD
C
L
= 15 pF; V
CC
= 5 V
V
I
= V
CC
or GND
C
L
= 50 pF; f = 1 MHz;
notes 1 and 2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74AHC273 | Octal D-type flip-flop with reset;positive-edge trigger(帶復(fù)位的八D觸發(fā)器；上升沿觸發(fā)) |
| 74AHC273PWDH | Octal D-type flip-flop with reset; positive-edge trigger |
| 74AHCT2G | Dual 2-input OR gate |
| 74AHC2G | Dual 2-input OR gate |
| 74AHC2G32 | Dual 2-input OR gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74AHCT273BQ | 制造商:NXP Semiconductors 功能描述:IC OCTAL D F-F POS EDGE 20DH |
| 74AHCT273BQ,115 | 功能描述:觸發(fā)器 OCTAL D FLIP-FLOP RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74AHCT273BQ-G | 功能描述:觸發(fā)器 OCTAL D FLIP-FLOP RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74AHCT273BQ-Q100X | 制造商:NXP Semiconductors 功能描述:Flip Flop D-Type Bus Interface Pos-Edge 1-Element 20-Pin DHVQFN EP T/R 制造商:NXP Semiconductors 功能描述:74AHCT273BQ-Q100/DHVQFN20/REEL - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC FLIP-FLOP OCTAL D 20DHVQFN |
| 74AHCT273D | 功能描述:觸發(fā)器 OCT D F/FW/RESET POS EDGE TR RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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