參數(shù)資料
型號(hào)： 74AHCT74
廠商： NXP Semiconductors N.V.
英文描述： Dual D-type flip-flop with set and reset; positive-edge trigger(帶置位和復(fù)位的雙D觸發(fā)器；上升沿觸發(fā)；)
中文描述： 雙D型觸發(fā)器設(shè)置和復(fù)位觸發(fā)器，積極邊緣觸發(fā)器（帶置位和復(fù)位的雙?觸發(fā)器，上升沿觸發(fā);）
文件頁數(shù)： 2/20頁
文件大?。?/td> 92K
代理商： 74AHCT74
1999 Sep 23
2
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74AHC74; 74AHCT74
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
Balanced propagation delays
Inputsacceptsvoltageshigherthan
V
CC
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Output capability: standard
I
CC
category: flip-flops
Specified from
40 to +85 and +125
°
C.
DESCRIPTION
The 74AHC/AHCT74 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
No. 7A.
The 74AHC/AHCT74 dual
positive-edge triggered, D-type
flip-flops with individual data (D)
inputs,clock (CP)inputs,set (S
D
)and
reset (R
D
) inputs; also
complementary Q and Q outputs.
The set and reset are asynchronous
active LOW inputs and operate
independently of the clock input.
Information on the data input is
transferred to the Q output on the
LOW-to-HIGH transition of the clock
pulse. The D inputs must be stable
one set-up time prior to the
LOW-to-HIGH clock transition for
predictable operation.
Schmitt-trigger action in the clock
input makes the circuit highly tolerant
to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
FUNCTION TABLES
Table 1
See note 1
Table 2
See note 1
Note to Tables 1 and 2
1.
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑
= LOW-to-HIGH CP transition;
Q
n+1
= state after the next LOW-to-HIGH CP transition.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay
nCP to nQ, nQ
nS
D
, nR
D
to nQ, nQ
max. clock frequency
input capacitance
power dissipation
capacitance
C
L
= 15 pF;
V
CC
= 5 V
3.7
3.7
130
3.3
3.7
100
4.0
16
ns
ns
MHz
pF
pF
f
max
C
I
C
PD
V
I
= V
CC
or GND 4.0
C
L
= 50 pF;
f = 1 MHz;
notes 1 and 2
12
INPUT
OUTPUT
nS
D
L
H
L
nR
D
H
L
L
nCP
nD
nQ
nQ
X
X
X
X
X
X
H
L
H
L
H
H
INPUT
OUTPUT
nS
D
H
H
nR
D
H
H
nCP
↑
↑
nD
nQ
n+1
L
H
nQ
n+1
H
L
L
H
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