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參數(shù)資料
| 型號(hào)： | 74ALS109A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual J-K positive edge-triggered flip-flop with set and reset |
| 中文描述： | 雙JK上升沿觸發(fā)器設(shè)置和復(fù)位觸發(fā)器 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 93K |
| 代理商： | 74ALS109A |
Philips Semiconductors
Product specification
74ALS109A
Dual J-K positive edge triggered flip-flop
with set and reset
1991 Feb 08
6
TEST CIRCUIT AND WAVEFORMS
t
w
90%
V
M
10%
90%
V
M
10%
90%
V
M
10%
90%
V
M
10%
NEGATIVE
PULSE
POSITIVE
PULSE
t
w
AMP (V)
0.3V
0.3V
t
THL (
t
f
f
)
INPUT PULSE REQUIREMENTS
Rep.Rate
t
w
t
TLH
2.0ns
t
THL
2.0ns
1MHz
500ns
Input Pulse Definition
V
CC
Family
74ALS
D.U.T.
PULSE
GENERATOR
R
L
C
L
R
T
V
IN
V
OUT
Test Circuit for Totem-pole Outputs
DEFINITIONS:
R
L
=
Load resistor;
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
OUT
of
pulse generators.
C
L
=
R
T
=
t
THL (
t
f
)
t
TLH (
t
r
)
t
TLH (
t
r
)
AMP (V)
Amplitude
3.5V
1.3V
V
M
SC00005
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ALS109AD | Dual J-K positive edge-triggered flip-flop with set and reset |
| 74ALS109AN | Dual J-K positive edge-triggered flip-flop with set and reset |
| 74ALS10A | Triple 3-Input NAND gate |
| 74ALS10AD | Triple 3-Input NAND gate |
| 74ALS10AN | Triple 3-Input NAND gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALS109AD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual J-K positive edge-triggered flip-flop with set and reset |
| 74ALS109AN | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual J-K positive edge-triggered flip-flop with set and reset |
| 74ALS109ANNSC91 | 制造商:National Semiconductor 功能描述:74ALS109N |
| 74ALS10A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple 3-Input NAND gate |
| 74ALS10AD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple 3-Input NAND gate |
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