參數(shù)資料
型號: 74ALVC08
廠商: NXP Semiconductors N.V.
英文描述: Quad 2-input AND gate
中文描述: 四2輸入與門
文件頁數(shù): 2/16頁
文件大?。?/td> 87K
代理商: 74ALVC08
2003 May 16
2
Philips Semiconductors
Product specification
Quad 2-input AND gate
74ALVC08
FEATURES
Wide supply voltage range from 1.65 to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74ALVC08 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall times.
The 74ALVC08 provides the 2-input AND function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay nA, nB to nY
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 k
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
1.9
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
2.2
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
2.0
2.7
ns
ns
ns
ns
pF
pF
C
I
C
PD
input capacitance
power dissipation capacitance per buffer
3.5
24
V
CC
= 3.3 V; notes 1 and 2
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