- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382821 > 74ALVC162373 (Fairchild Semiconductor Corporation) Triple 3-Input Positive-NAND Gates 14-SO -40 to 85 PDF資料下載
參數(shù)資料
| 型號： | 74ALVC162373 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Triple 3-Input Positive-NAND Gates 14-SO -40 to 85 |
| 中文描述： | 低電壓16位透明鎖存器，在3.6V耐壓輸入和輸出，在輸出26з串聯(lián)電阻 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 95K |
| 代理商： | 74ALVC162373 |
www.fairchildsemi.com
2
7
Connection Diagram
Truth Tables
H
L
X
Z
O
0
=
Previous O
0
before HIGH-to-LOW of Latch Enable
=
HIGH Voltage Level
=
LOW Voltage Level
=
Immaterial (HIGH or LOW, inputs may not float)
=
High Impedance
Functional Description
The 74ALVC162373 contains sixteen edge D-type latches
with 3-STATE outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LE
n
) input is HIGH, data on
the I
n
enters the latches. In this condition the latches are
transparent, i.e., a latch output will change state each time
its I input changes. When LE
n
is LOW, the latches store
information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition on LE
n
. The
3-STATE outputs are controlled by the Output Enable
(OE
n
) input. When OE
n
is LOW the standard outputs are in
the 2-state mode. When OE
n
is HIGH, the standard outputs
are in the high impedance mode but this does not interfere
with entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Outputs
LE
1
OE
1
I
0
–I
7
O
0
–O
7
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O
0
Inputs
Outputs
LE
2
OE
2
I
8
–I
15
O
8
–O
15
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ALVC162373T | Triple 3-Input Positive-NAND Gates 14-TSSOP -40 to 85 |
| 74ALVC16821 | Triple 3-Input Positive-AND Gates 14-TSSOP -40 to 85 |
| 74ALVC16821MTD | Triple 3-Input Positive-AND Gates 14-TSSOP -40 to 85 |
| 74ALVC16821MTDX | 20-Bit D-Type Flip-Flop |
| 74ALVC16827 | Triple 3-Input Positive-AND Gates 14-TSSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALVC162373T | 功能描述:閉鎖 16-Bit Transparent L RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74ALVC162373T_Q | 功能描述:閉鎖 16-Bit Transparent L RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74ALVC162373TX | 功能描述:閉鎖 Transparent Latch LV 16Bit RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74ALVC162374 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs and 26з Series Resistors in Outputs |
| 74ALVC162374T | 功能描述:觸發(fā)器 16-Bit D-Type Flip-F RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。