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參數(shù)資料
| 型號： | 74ALVC16835 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Triple 3-Input Positive-AND Gates 14-TSSOP -40 to 85 |
| 中文描述： | 低電壓18位通用總線容錯與3.6V的輸入和輸出驅(qū)動器 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 88K |
| 代理商： | 74ALVC16835 |
2002 Fairchild Semiconductor Corporation
DS500645
www.fairchildsemi.com
September 2001
Revised February 2002
7
74ALVC16835
Low Voltage 18-Bit Universal Bus Driver
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16835 low voltage 18-bit universal bus driver
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is tog-
gled. Data transfers from the Inputs (I
n
) to Ouputs (O
n
) on a
Positive Edge Transition of the Clock. When OE is LOW,
the output data is enabled. When OE is HIGH the output
port is in a high impedance state.
The 74ALVC16835 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V.
The 74ALVC16835 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
I
Compatible with PC100 DIMM module specifications
I
1.65V to 3.6V V
CC
supply operation
I
3.6V tolerant inputs and outputs
I
t
PD
(CLK to O
n
)
4.5 ns max for 3.0V to 3.6V V
CC
5.5 ns max for 2.3V to 2.7V V
CC
9.2 ns max for 1.65V to 1.95V V
CC
I
Power-off high impedance inputs and outputs
I
Supports live insertion/withdrawal (Note 1)
I
Latchup conforms to JEDEC JED78
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
(OE to GND) through a pulldown resistor;
the minimum value of the resistor is determined by the current sourcing
capability of the driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
Package
Number
MTD56
Package Description
74ALVC16835MTD
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALVC16835A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:18-bit registered driver 3-State |
| 74ALVC16835ADG | 功能描述:總線收發(fā)器 18-BIT REG DRVR 3-S RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ALVC16835ADGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:18-bit registered driver 3-State |
| 74ALVC16835ADGG,11 | 功能描述:總線收發(fā)器 18-BIT REG DRVR 3-S RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ALVC16835ADGG,112 | 制造商:NXP Semiconductors 功能描述: |
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