VM VOH
參數(shù)資料
型號: 74ALVC16835DGGRE4
廠商: Texas Instruments
文件頁數(shù): 14/16頁
文件大?。?/td> 0K
描述: IC UNIV BUS DVR 18BIT 56TSSOP
標(biāo)準(zhǔn)包裝: 2,000
系列: 74ALVC
邏輯類型: 通用總線驅(qū)動器
電路數(shù): 18 位
輸出電流高,低: 24mA,24mA
電源電壓: 1.65 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 帶卷 (TR)
www.ti.com
PARAMETER MEASUREMENT INFORMATION
VM
VOH
VOL
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
Open
GND
RL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + V
VOH V
0 V
VI
0 V
tw
VI
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 .
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
0 V
VI
VM
tPHL
VM
VI
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VM
tPLH
VLOAD
VLOAD/2
1.8 V
2.5 V
± 0.2 V
2.7 V
3.3 V
± 0.3 V
1 k
500
500
500
VCC
RL
2
× VCC
2
× VCC
6 V
VLOAD
CL
30 pF
50 pF
0.15 V
0.3 V
V
VCC
2.7 V
VI
VCC/2
1.5 V
VM
tr/tf
≤2 ns
≤2.5 ns
INPUT
SN74ALVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES125J – FEBRUARY 1998 – REVISED NOVEMBER 2004
Figure 1. Load Circuit and Voltage Waveforms
7
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