參數(shù)資料
型號(hào)： 74ALVCH32501EC
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： 36-bit universal bus transceiver with direction pin; 5 V tolerant; 3-state
中文描述： ALVC/VCX/A SERIES, DUAL 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PBGA114
封裝： 16 X 5.50 MM, 1.05 MM HEIGHT, PLASTIC, SOT-537-1, LFBGA-114
文件頁(yè)數(shù)： 2/16頁(yè)
文件大?。?/td> 88K
代理商： 74ALVCH32501EC
2000 Mar 16
2
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
FEATURES
3-state non-inverting outputs for bus oriented
applications
Wide supply voltage range of 1.2 to 3.6 V
Complies with JEDEC standard no. 8-1A
Current drive
±
24 mA at 3.0 V
Universal bus transceiver with D-type latches and
D-type flip-flops capable of operating in transparent,
latched or clocked mode
CMOS low power consumption
Direct interface with TTL levels
All inputs have bus-hold circuitry
Output drive capability 50
transmission lines at 85
°
C
Plastic fine-pitch ball grid array package.
DESCRIPTION
The 74ALVCH32501 is a high-performance CMOS
product designed for V
CC
operation at 2.5 and 3.3 V with
I/O compatibility up to 5 V.
Active bus-hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
The 74ALVCH32501 can be used as two 18-bit
transceivers or one 36-bit transceiver featuring
non-inverting 3-state bus compatible outputs in both send
and receive directions. Data flow in each direction is
controlledbyoutputenable(OE
AB
andOE
BA
),latchenable
(LE
AB
and LE
BA
), and clock inputs (CP
AB
and CP
BA
).
For A-to-B data flow, the device operates in the
transparent mode when LE
AB
is HIGH. When input LE
AB
is
LOW, the A data is latched if input CP
AB
is held at a HIGH
or LOW level. If input LE
AB
is LOW, the A data is stored in
the latch/flip-flop on the LOW-to-HIGH transition of CP
AB
.
When input OE
AB
is HIGH, the outputs are active. When
input OE
AB
is LOW, the outputs are in the high-impedance
state.
Data flow for B-to-A is similar to that of A-to-B, but uses
inputs OE
BA
, LE
BA
and CP
BA
. The output enables are
complimentary (OE
AB
is active HIGH, and OE
BA
is active
LOW).
To ensure the high-impedance state during power-up or
power-down, pin OE
BA
should be tied to V
CC
through a
pull-up resistor and pin OE
AB
should be tied to GND
through a pull-down resistor. The minimum value of the
resistor is determined by the current-sinking or
current-sourcing capability of the driver.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns.
Note
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
t
PHL
/t
PLH
propagation delay A
n
to B
n
; B
n
to A
n
C
L
= 30 pF; V
CC
= 2.5 V
C
L
= 50 pF; V
CC
= 3.3 V
2.8
3.0
4.0
8.0
ns
ns
pF
pF
C
I
C
I/O
C
PD
input capacitance
input/output capacitance
power dissipation capacitance per latch
V
I
= GND to V
CC
; note 1
outputs enabled
outputs disabled
21
3
pF
pF
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