參數(shù)資料
型號: 74ALVCHS162830DGB;
廠商: NXP Semiconductors
文件頁數(shù): 8/10頁
文件大?。?/td> 0K
描述: IC ADDRESS DVR 18-36BIT 80TSSOP
標準包裝: 700
系列: 74ALVCHS
邏輯類型: 18 位至 36 位地址驅動器
元件數(shù): 2
每個元件的位元數(shù): 9
輸出電流高,低: 12mA,12mA
電源電壓: 2.3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 80-TFSOP (0.240",6.10mm 寬)
供應商設備封裝: 80-TSSOP
包裝: 管件
其它名稱: 935270264112
ALVCHS162830GB
ALVCHS162830GB-ND
Philips Semiconductors
Product data
74ALVCHS162830
18-bit to 36-bit address driver with bus hold
(3-State)
2001 Sep 07
7
From Output
Under Test
Load Circuit
Open
GND
TEST
S1
tpd
tPLZ/tPZL
Open
2
× VCC
tPHZ/tPZH
GND
SV01849
500
CL = 30 pF
(see Note A)
500
2
× VCC
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
Timing
Input
VCC/2
VCC
0 V
VCC
0 V
VCC/2
tsu
th
Voltage Waveforms
Setup and Hold Times
VCC
0 V
VCC/2
tw
Data
Input
Voltage Waveforms
Pulse Duration
VCC
0 V
Input
VCC/2
tPLH
VOH
VOL
VCC/2
tPHL
Output
Voltage Waveforms
Propagation Delay Times
VCC
0 V
Output
Control
(low-level
enabling)
VCC/2
VCC
VOL
VOL + 0.15 V
tPZL
tPLZ
VCC/2
VOH
0 V
VOH – 0.15 V
VCC/2
tPZH
tPHZ
Voltage Waveforms
Enable and Disable Times
Output
Waveform 1
S1 at 2 x VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
S1
NOTES:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 , tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load circuit and voltage waveforms
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74ALVCHS16830 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:18-bit to 36-bit address driver with bus hold (3-State)