參數(shù)資料
型號： 74ALVCHT16835DGV,1
廠商： NXP Semiconductors
文件頁數(shù)： 5/12頁
文件大?。?/td> 0K
描述： IC REGISTERED DVR 16BIT 56TVSOP
產(chǎn)品培訓(xùn)模塊： Logic Packages
標(biāo)準(zhǔn)包裝： 2,500
系列： 74ALVCHT
邏輯類型： 緩沖器/線路驅(qū)動器，非反相
元件數(shù)： 1
每個元件的位元數(shù)： 18
輸出電流高，低： 24mA，24mA
電源電壓： 2.3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-TFSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 56-TSSOP
包裝： 帶卷 (TR)
其它名稱： 935271855118
ALVCHT16835ADGV-T
ALVCHT16835ADGV-T-ND
Philips Semiconductors
Product data
74ALVCHT16835
18-bit registered driver (3-State)
2
2002 Jun 05
853-2350 28376
FEATURES
Wide supply voltage range of 2.3 V to 3.6 V
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive ± 24 mA at 3.0 V
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple V
CC and GND pins for minimum noise
and ground bounce
Output drive capability 50 transmission lines @ 85 °C
ESD protection exceeds 1500 V HBM per JESD22-A114, A115
and 1000 V CDM per JESD22-C101
Bus hold on data inputs eliminates the need for external
pullup/pulldown resistors
DESCRIPTION
The 74ALVCHT16835 is a 18-bit registered driver. Data flow is
controlled by active low output enable (OE), active high latch enable
(LE) and clock inputs (CP).
When LE is HIGH, the A to Y data flow is transparent. When LE is
LOW and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A-data is stored in the
latch/flip-flop.
When OE is LOW the outputs are active. When OE is HIGH, the
outputs go to the high impedance OFF-state. Operation of the OE
input does not affect the state of the latch/flip-flop.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
NC
Y1
Y2
Y3
Y4
Y5
Y6
GND
VCC
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
OE
LE
GND
NC
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
CP
GND
SH00188
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
An to Yn;
LE to Yn;
CP to Yn
VCC = 3.3 V, CL = 50 pF
2.3
2.7
2.2
ns
fmax
Maximum clock frequency
VCC = 3.3 V, CL = 50 pF
350
MHz
CI
Input capacitance
4.0
pF
CI/O
Input/Output capacitance
8.0
pF
C
Power dissipation capacitance per buffer
V = GND to VCC1
transparent mode
Output enabled
Output disabled
13
3
pF
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
Clocked mode
Output enabled
Output disabled
22
15
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
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