Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I
IH
/I
IL
Output I
OH
/I
OL
HIGH/LOW
I
0a
–I
0d
I
1a
–I
1d
E
S
Z
a
–Z
d
Source 0 Data Inputs
Source 1 Data Inputs
Enable Input (Active LOW)
Select Input
Outputs
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
20
m
A/
b
0.6 mA
20
m
A/
b
0.6 mA
20
m
A/
b
0.6 mA
20
m
A/
b
0.6 mA
b
1 mA/20 mA
Functional Description
The ’F157A is a quad 2-input multiplexer. It selects four bits
of data from two sources under the control of a common
Select input (S). The Enable input (E) is active LOW. When
E is HIGH, all of the outputs (Z) are forced LOW regardless
of all other inputs. The ’F157A is the logic implementation of
a 4-pole, 2-position switch where the position of the switch
is determined by the logic levels supplied to the Select in-
put. The logic equations for the outputs are shown below:
Z
n
e
E
#
(I
1n
S
a
I
0n
S)
A common use of the ’F157A is the moving of data from two
groups of registers to four common output busses. The par-
ticular register from which the data comes is determined by
the state of the Select input. A less obvious use is as a
function generator. The ’F157A can generate any four of the
16 different functions of two variables with one variable
common. This is useful for implementing highly irregular
logic.
Truth Table
Inputs
Output
E
S
I
0
I
1
Z
H
L
L
L
L
X
H
H
L
L
X
X
X
L
H
X
L
H
X
X
L
L
H
L
H
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Logic Diagram
TL/F/9483–4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2