- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369302 > 74F161A (National Semiconductor Corporation) Synchronous Presettable Binary Counter(同步可預(yù)置的二進(jìn)制計(jì)數(shù)器) PDF資料下載
參數(shù)資料
| 型號(hào)： | 74F161A |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous Presettable Binary Counter(同步可預(yù)置的二進(jìn)制計(jì)數(shù)器) |
| 中文描述： | 同步可預(yù)置二進(jìn)制計(jì)數(shù)器（同步可預(yù)置的二進(jìn)制計(jì)數(shù)器） |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 197K |
| 代理商： | 74F161A |
Functional Description
The ’F161A and ’F163A count in modulo-16 binary se-
quence. From state 15 (HHHH) they increment to state 0
(LLLL). The clock inputs of all flip-flops are driven in parallel
through a clock buffer. Thus all changes of the Q outputs
(except due to Master Reset of the ’F161A) occur as a re-
sult of, and synchronous with, the LOW-to-HIGH transition
of the CP input signal. The circuits have four fundamental
modes of operation, in order of precedence: asynchronous
reset (’F161A), synchronous reset (’F163A), parallel load,
count-up and hold. Five control inputsDMaster Reset (MR,
’F161A), Synchronous Reset (SR, ’F163A), Parallel Enable
(PE), Count Enable Parallel (CEP) and Count Enable Trickle
(CET)Ddetermine the mode of operation, as shown in the
Mode Select Table. A LOW signal on MR overrides all other
inputs and asynchronously forces all outputs LOW. A LOW
signal on SR overrides counting and parallel loading and
allows all outputs to go LOW on the next rising edge of CP.
A LOW signal on PE overrides counting and allows informa-
tion on the Parallel Data (P
n
) inputs to be loaded into the
flip-flops on the next rising edge of CP. With PE and MR
(’F161A) or SR (’F163A) HIGH, CEP and CET permit count-
ing when both are HIGH. Conversely, a LOW signal on ei-
ther CEP or CET inhibits counting.
The ’F161A and ’F163A use D-type edge triggered flip-flops
and changing the SR, PE, CEP and CET inputs when the CP
is in either state does not cause errors, provided that the
recommended setup and hold times, with respect to the ris-
ing edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is HIGH
and the counter is in state 15. To implement synchronous
multi-stage counters, the TC outputs can be used with the
CEP and CET inputs in two different ways. Please refer to
the ’F568 data sheet. The TC output is subject to decoding
spikes due to internal race conditions and is therefore not
recommended for use as a clock or asynchronous reset for
flip-flops, counters or registers.
Logic Equations: Count Enable
e
CEP
#
CET
#
PE
TC
e
Q
0
#
Q
1
#
Q
2
#
Q
3
#
CET
Mode Select Table
*
SR
PE
CET
CEP
Action on the Rising
Clock Edge (
L
)
L
H
H
H
H
X
L
H
H
H
X
X
H
L
X
X
X
H
X
L
Reset (Clear)
Load (P
n
Q
n
)
Count (Increment)
No Change (Hold)
No Change (Hold)
*
For ’F163A only
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
State Diagram
TL/F/9486–5
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74F161ASC | Synchronous Presettable Binary Counter |
| 74F161ASJ | Synchronous Presettable Binary Counter |
| 74F163APC | Synchronous Presettable Binary Counter |
| 74F163ASC | Synchronous Presettable Binary Counter |
| 74F163ASJ | Synchronous Presettable Binary Counter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F161A_07 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Synchronous Presettable Binary Counter |
| 74F161AD SIG 92 | 制造商:n/a 功能描述:74F161 S8G2B |
| 74F161ADC | 制造商: 功能描述: 制造商:FCS 功能描述: 制造商:Texas Instruments 功能描述: |
| 74F161ADSIG92 | 制造商:n/a 功能描述:74F161 S8G2B |
| 74F161ALC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。