![](http://datasheet.mmic.net.cn/230000/74F164_datasheet_15562957/74F164_4.png)
Philips Semiconductors
Product specification
74F164
8-bit serial-in parallel-out shift register
1995 Sep 22
4
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
CONDITIONS
1
MIN
TYP
2
MAX
V
OH
High-level output voltage
High-level out ut voltage
V
= MIN, V
= MAX,
CC
V
IH
= MIN, I
OH
= MAX
±
10%V
CC
±
5%V
CC
±
10%V
CC
±
5%V
CC
2.5
V
IL
2.7
3.4
V
V
OL
Low-level output voltage
V
= MIN, V
= MAX,
CC
V
IH
= MIN, I
OL
= MAX
0.30
0.50
V
IL
0.30
0.50
V
V
IK
I
I
I
IH
I
ILL
I
OS
I
CC
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
V
CC
= MAX
–0.73
–1.2
V
Input current at maximum input voltage
100
μ
A
μ
A
High-level input current
20
Low-level input current
–0.6
mA
Short-circuit output current
3
-60
–150
mA
Supply current (total)4
33
55
mA
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter test, I
OS
tests should be performed last.
4. Measure I
CC
with the serial inputs grounded, the clock input at 2.4V, and a momentary ground, then applied to Master Reset, and all outputs
open.
APPLICATION
RESET
CLOCK
DATA
ENABLE
Dsa
Dsb
Dsa
Dsb
CP
MR
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11 D12 D13 D14 D15
CP
MR
H
74F164
74F164
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SF00716
The 74F164 can be cascaded to form synchronous shift registers of longer length.
Here, two devices are combined to form a 16-bit shift register.