參數(shù)資料
型號: 74F169SC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: 4-Stage Synchronous Bidirectional Counter
中文描述: F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16
封裝: 0.150 INCH, MS-012, SOIC-16
文件頁數(shù): 3/12頁
文件大小: 116K
代理商: 74F169SC
Philips Semiconductors
Product specification
74F169
4-bit up/down binary synchronous counter
1996 Jan 05
3
LOGIC SYMBOL
9
3
4
5
6
15
11
12
13
14
1
2
7
10
CP
CEP
CET
PE
D
0
D
1
D
2
D
3
Q
0
Q
1
Q
2
Q
3
TC
U/D
SF00786
V
= Pin 16
GND = Pin 8
LOGIC SYMBOL (IEEE/IEC)
M4 [DOWN]
9
1
10
7
2
[1]
3
4
5
6
1, 7D
14
13
12
11
M1 [LOAD]
SF00787
M2 [COUNT]
M3 [UP]
CTR DIV 16
[2]
[4]
[8]
15
3, 5 CT=15
4, 5 CT=0
G5
G6
2, 3, 5, 6+/C7
2, 4, 5, 6–
FUNCTIONAL DESCRIPTION
The 74F169 uses edge-triggered J-K-type flip-flops and have no
constraints on changing the control or data input signals in either
state of the clock. The only requirement is that the various inputs
attain the desired state at least a setup time before the rising edge
of the clock and remain valid for the recommended hold time
thereafter. The parallel load operation takes precedence over the
other operations, as indicated in the Mode Select Table. When PE is
Low, the data on the D
0
- D
3
inputs enter the flip-flops on the next
rising edge of the Clock. In order for counting to occur, both CEP
and CET must be Low and PE must be High; the U/D input
determines the direction of counting. The Terminal Count (TC)
output is normally High and goes Low, provided that CET is Low,
when a counter reaches zero in the Count Down mode or reaches
15 in the Count Up mode. The TC output state is not a function of
the Count Enable Parallel (CEP) input level. Since the TC signal is
derived by decoding the flip-flop states, there exists the possibility of
decoding spikes on TC. For this reason the use of TC as a clock
signal is not recommended (see logic equations below).
1) Count Enable = CEP
CET
PE
2) Up: TC = Q
0
Q
3
(U/D)
CET
3) Down: TC = Q
0
Q
1
Q
2
Q
3
(U/D)
CET
MODE SELECT — FUNCTION TABLE
INPUTS
OUTPUTS
Q
n
L
H
OPERATING MODE
CP
U/D
CEP
CET
PE
D
n
l
X
TC
X
X
X
X
X
X
l
(1)
(1)
Parallel load (Dn
Qn)
X
h
l
l
h
X
Count Up
(1)
Count Up (increment)
l
l
l
h
X
Count Down
(1)
Count Down (decrement)
X
X
h
X
X
X
h
h
X
X
q
n
q
n
(1)
H
Hold (do nothing)
H = High voltage level steady state
h = High voltage level one setup time prior to the Low-to-High clock transition
L = Low voltage level steady state
l
= Low voltage level one setup time prior to the Low-to-High clock transition
q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition
X = Don’t care
= Low-to-High clock transition
(1)= The TC is Low when CET is Low and the counter is at Terminal Count.
Terminal Count Up is (HHHH) and Terminal Count Down is (LLLL).
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