參數(shù)資料
型號: 74F190PC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Up/Down Decade Counter with Preset and Ripple Clock
中文描述: F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, PDIP16
封裝: 0.300 INCH, PLASTIC, MS-001, DIP-16
文件頁數(shù): 2/10頁
文件大?。?/td> 178K
代理商: 74F190PC
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I
IH
/I
IL
Output I
OH
/I
OL
HIGH/LOW
CE
CP
P
0
–P
3
PL
U/D
Q
0
–Q
3
RC
TC
Count Enable Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Parallel Data Inputs
Asynchronous Parallel Load Input (Active LOW)
Up/Down Count Control Input
Flip-Flop Outputs
Ripple Clock Output (Active LOW)
Terminal Count Output (Active HIGH)
1.0/3.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
50/33.3
50/33.3
20
m
A/
b
1.8 mA
20
m
A/
b
0.6 mA
20
m
A/
b
0.6 mA
20
m
A/
b
0.6 mA
20
m
A/
b
0.6 mA
b
1 mA/20 mA
b
1 mA/20 mA
b
1 mA/20 mA
Functional Description
The ’F190 is a synchronous up/down BCD decade counter
containing four edge-triggered flip-flops, with internal gating
and steering logic to provide individual preset, count-up and
count-down operations. It has an asynchronous parallel
load capability permitting the counter to be preset to any
desired number. When the Parallel Load (PL) input is LOW,
information present on the Parallel Data inputs (P
0
–P
3
) is
loaded into the counter and appears on the Q outputs. This
operation overrides the counting functions, as indicated in
the Mode Select Table. A HIGH signal on the CE input inhib-
its counting. When CE is LOW, internal state changes are
initiated synchronously by the LOW-to-HIGH transition of
the clock input. The direction of counting is determined by
the U/D input signal, as indicated in the Mode Select Table,
CE and U/D can be changed with the clock in either state,
provided only that the recommended setup and hold times
are observed.
RC Truth Table
Two types of outputs are provided as overflow/underflow
indicators. The Terminal Count (TC) output is normally LOW
and goes HIGH when a circuit reaches zero in the count-
down mode or reaches 9 in the count-up mode. The TC
output will then remain HIGH until a state change occurs,
whether by counting or presetting or until U/D is changed.
The TC output should not be used as a clock signal be-
cause it is subject to decoding spikes. The TC signal is also
used internally to enable the Ripple Clock (RC) output. The
RC output is normally HIGH. When CE is LOW and TC is
HIGH, the RC output will go LOW when the clock next goes
LOW and will stay LOW until the clock goes HIGH again.
This feature simplifies the design of multistage counters.
For a discussion and illustrations of the various methods of
implementing multistage counters, please see the ’F191
data sheet.
Inputs
Output
CE
TC
*
CP
RC
L
H
X
H
X
L
X
X
H
H
*
TC is generated internally
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
L
e
LOW-to-HIGH Clock Transition
e
LOW Pulse
Mode Select Table
Inputs
Mode
PL
CE
U/D
CP
H
H
L
H
L
L
X
H
L
H
X
X
L
L
X
X
Count Up
Count Down
Preset (Asyn.)
No Change (Hold)
State Diagram
TL/F/9494–5
2
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