參數(shù)資料
型號(hào): 74F350
廠商: NXP Semiconductors N.V.
英文描述: 4-bit shifter
中文描述: 4位移位
文件頁數(shù): 5/6頁
文件大?。?/td> 64K
代理商: 74F350
Philips Semiconductors FAST Products
Product specification
74F350
4-bit shifter
March 20, 1989
5
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
TYP
2
UNIT
MIN
MAX
V
OH
High-level output voltage
V
CC
= MIN, V
IL
= MAX
±
10%V
CC
2.4
V
V
IH
= MIN, I
OH
= MAX
±
5%V
CC
2.7
3.4
V
OL
Low-level output voltage
V
CC
= MIN, V
IL
= MAX
±
10%V
CC
0.35
0.50
V
V
IH
= MIN, I
OL
= MAX
±
5%V
CC
0.35
0.50
V
IK
I
I
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
–0.73
–1.2
V
Input current at maximum input voltage
100
μ
A
I
IH
High-level input current
V
CC
= MAX, V
I
= 2.7V
20
μ
A
I
IL
Low-level input current
V
CC
= MAX, V
I
= 0.5V
–1.2
mA
I
OZH
Off-state output current,
High-level voltage applied
V
CC
= MAX, V
O
= 2.7V
50
μ
A
I
OZL
Off-state output current,
Low-level voltage applied
V
CC
= MAX, V
O
= 0.5V
–50
μ
A
I
OS
Short-circuit output current
3
V
CC
= MAX
–60
–150
mA
I
CC
Supply current (total)
I
CCH
V
CC
= MAX
22
35
mA
I
CCL
26
41
mA
I
CCZ
26
42
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST
CONDITION
LIMITS
UNIT
V
CC
= +5.0V
T
amb
= +25
°
C
C
L
= 50pF, R
L
= 500
V
CC
= +5.0V
±
10%
T
amb
= 0
°
C to +70
°
C
C
L
= 50pF, R
L
= 500
MIN
TYP
MAX
MIN
MAX
t
PLH
t
PHL
Propagation delay
In to Yn
Waveform 1
3.0
2.5
4.5
4.0
6.0
5.5
3.0
2.5
7.0
6.5
ns
t
PLH
t
PHL
Propagation delay
Sn to Yn
Waveform 1
4.0
3.0
7.8
6.5
10.0
8.5
4.0
3.0
11.0
9.5
ns
t
PZH
t
PZL
Output Enable time to
High or Low level
Waveform 2
Waveform 3
2.5
4.0
5.0
7.0
7.0
9.0
2.5
4.0
8.0
10.0
ns
t
PHZ
t
PLZ
Output Disable time to
High or Low level
Waveform 2
Waveform 3
2.0
2.0
3.9
4.0
5.5
5.5
2.0
2.0
6.5
6.5
ns
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