參數(shù)資料
型號: 74F373
廠商: NXP Semiconductors N.V.
英文描述: Octal transparent latch (3-State)(八透明鎖存器(三態(tài)))
中文描述: 八路透明鎖存器(3態(tài))(八透明鎖存器(三態(tài)))
文件頁數(shù): 6/12頁
文件大小: 93K
代理商: 74F373
Philips Semiconductors
Product specification
74F373/74F374
Latch/flip-flop
December 5, 1994
6
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
TYP
2
UNIT
CONDITIONS
1
MIN
MAX
V
OH
High level output voltage
High-level output voltage
V
CC
= MIN, V
IL
= MAX,
±
10%V
CC
2.4
V
V
IH
= MIN, I
OH
= MAX
±
5%V
CC
2.7
3.4
V
V
OL
Low level output voltage
Low-level output voltage
V
CC
= MIN, V
IL
= MAX,
V
IH
= MIN, I
OL
= MAX
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
±
10%V
CC
±
5%V
CC
0.35
0.50
V
0.35
0.50
V
V
IK
I
I
I
IH
I
IL
Input clamp voltage
Input current at maximum input voltage
High-level input current
Low-level input current
-0.73
-1.2
100
20
-0.6
V
μ
A
μ
A
mA
I
OZH
Off-state output current, high-level voltage applied
V
CC
= MAX, V
O
= 2.7V
50
μ
A
I
OZL
Off-state output current, low-level voltage applied
V
CC
= MAX, V
O
= 0.5V
-50
μ
A
I
OS
Short-circuit output current
3
V
CC
= MAX
-60
-150
mA
I
CC
Supply current (total)
74F373
V
CC
= MAX
35
60
mA
74F374
57
86
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
amb
= +25
°
C
V
CC
= +5.0V
C
L
= 50pF, R
L
= 500
MIN
TYP
T
amb
= 0
°
C to +70
°
C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500
MIN
SYMBOL
PARAMETER
TEST
UNIT
CONDITION
MAX
MAX
t
PLH
t
PHL
Propagation delay
Dn to Qn
Waveform 3
3.0
2.0
5.3
3.7
7.0
5.0
3.0
2.0
8.0
6.0
ns
t
PLH
t
PHL
t
PZH
t
PZL
Propagation delay
E to Qn
74F373
Waveform 2
5.0
3.0
9.0
4.0
11.5
7.0
5.0
3.0
12.0
8.0
ns
Output enable time
to high or low level
Waveform 6
Waveform 7
2.0
2.0
5.0
5.6
11.0
7.5
2.0
2.0
11.5
8.5
ns
t
PHZ
t
PLZ
Output disable time
from high or low level
Waveform 6
Waveform 7
2.0
2.0
4.5
3.8
6.5
5.0
2.0
2.0
7.0
6.0
ns
f
max
t
PLH
t
PHL
Maximum clock frequency
Waveform 1
150
165
140
ns
Propagation delay
CP to Qn
74F374
Waveform 1
3.5
3.5
5.0
5.0
7.5
7.5
3.0
3.0
8.5
8.5
ns
t
PZH
t
PZL
Output enable time
to high or low level
Waveform 6
Waveform 7
2.0
2.0
9.0
5.3
11.0
7.5
2.0
2.0
12.0
8.5
ns
t
PHZ
t
PLZ
Output disable time
from high or low level
Waveform 6
Waveform 7
2.0
2.0
5.3
4.3
6.0
5.5
2.0
2.0
7.0
6.5
ns
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