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參數(shù)資料
| 型號： | 74F525QCX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Programmable Counter |
| 中文描述： | F/FAST SERIES, ASYN POSITIVE EDGE TRIGGERED DOWN DIVIDE BY N COUNTER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 184K |
| 代理商： | 74F525QCX |
Timing Diagrams
(Continued)
TL/F/9547–8
FIGURE 4. MODE 6
M
n
e
110
j
With XTR HIGH, the rising edge of CP loads data from the latches to the counter.
k
With XTR LOW, the rising edge of CP begins the count, and Q goes HIGH.
l
When the count reaches zero, Q goes LOW, and Q/2 toggles state. Bringing XTR HIGH before count reaches zero will reload the counter, but not affect Q.
Notes:
Loading N
e
0 halts counter; loading N
e
1 will result in undefined operation.
Pulse width
e
(2/CP)
*
(N
b
1)
TL/F/9547–9
FIGURE 5. MODE 7
M
n
e
111
j
With XTR HIGH, the rising edge of CP, loads data from the latches to the counter.
k
On the falling edge of XTR, the rising edge of CP begins count-down.
l
When count reaches zero, Q goes HIGH for one period of CP, and Q/2 toggles on the Q rising edge.
m
On the rising edge of CP on which Q goes LOW, the counters are reloaded.
n
Count-down begins again.
5
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