參數(shù)資料
型號(hào): 74F8961
廠商: NXP Semiconductors N.V.
英文描述: Octal latched bidirectional Futurebus transceivers 3-State open-collector
中文描述: 八進(jìn)制鎖存雙向Futurebus收發(fā)器三態(tài)開(kāi)路集電極
文件頁(yè)數(shù): 5/11頁(yè)
文件大?。?/td> 194K
代理商: 74F8961
Philips Semiconductors FAST Products
Product specification
74F8960/74F8961
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
December 19, 1990
5
FUNCTION TABLE FOR 74F8960
INPUTS
LATCH
OUTPUTS
OPERATING MODE
An
Bn*
LE
OEA
OEB
0
L
OEB
1
L
STATE
An
Bn
H
X
L
L
H
Z
L
A 3–state, data from A to B
L
X
L
L
L
L
L
Z
H**
X
X
H
L
L
L
Qn
Z
Qn
A 3–state, latched data to B
L
H
L
L
(1)
(1)
(1)
Feedback: A to B, B to A
H
H
H
L
L
H (2)
H
Z(2)
Preconditioned latch enabling data transfer from B to A
L
H
H
L
L
H (2)
L
Z(2)
H
H
L
L
Qn
Qn
Qn
Latch state to A and B
H
X
L
L
H
X
H
Z
Z
l
X
L
L
H
X
l
Z
Z
B and A 3–state
X
X
H
L
H
X
Qn
Z
Z
H
L
H
H
X
H
H
Z
L
L
H
H
H
L
L
Z
B 3–state, data from B to A
H
H
H
H
H
Qn
H
Z
L
H
H
H
H
Qn
L
Z
H
X
L
L
X
H
H
Z
Z
l
X
L
L
X
H
l
Z
Z
B and A 3–state
X
X
H
L
X
H
Qn
Z
Z
H
L
H
X
H
H
H
Z
L
L
H
X
H
L
L
Z
B 3–state, data from B to A
H
H
H
X
H
Qn
H
Z
L
H
H
X
H
Qn
L
Z
NOTES:
1. H =
2. L
3. X =
4. –
5. Z =
6. Q
n
=
7. (1) =
8. (2) =
9. H**=
10.B* =
High–voltage level
Low–voltage level
Don’t care
Input not externally driven
High impedance (off) state
High or low voltage level one setup time prior to the low–to–high LE transition.
Condition will cause a feedback loop path: A to B and B to A.
The latch must be preconmditioned such that B inputs may assume a high or low level while OEB0 and OEB1 are low and LE is high.
Goes to level of pullup voltage.
Precaution should be taken to insure the B inputs do not float. If they do they are equal to low state.
=
=
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PDF描述
74F8960 Octal latched bidirectional Futurebus transceivers(3-State + open-collector)(八鎖存雙向預(yù)置總線收發(fā)器(三態(tài)+開(kāi)啟集電極))
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