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參數(shù)資料
| 型號(hào)： | 74HC109DB,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 2/9頁 |
| 文件大小： | 0K |
| 描述： | IC DUAL JK F-F POS-EDGE 16-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 1,092 |
| 系列： | 74HC |
| 功能： | 設(shè)置（預(yù)設(shè)）和復(fù)位 |
| 類型： | JK 型 |
| 輸出類型： | 差分 |
| 元件數(shù)： | 2 |
| 每個(gè)元件的位元數(shù)： | 1 |
| 頻率 - 時(shí)鐘： | 81MHz |
| 延遲時(shí)間 - 傳輸： | 9ns |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 2 V ~ 6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.209"，5.30mm 寬） |
| 包裝： | 管件 |
1997 Nov 25
2
Philips Semiconductors
Product specication
Dual JK ip-op with set and reset;
positive-edge trigger
74HC/HCT109
FEATURES
J, K inputs for easy D-type flip-flop
Toggle flip-flop or “do nothing” mode
Output capability: standard
ICC category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT109 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT109 are dual positive-edge triggered, JK
flip-flops with individual J, K inputs, clock (CP) inputs, set
(SD) and reset (RD) inputs; also complementary Q and Q
outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input.
The J and K inputs control the state changes of the
flip-flops as described in the mode select function table.
The J and K inputs must be stable one set-up time prior to
the LOW-to-HIGH clock transition for predictable
operation.
The JK design allows operation as a D-type flip-flop by
tying the J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CL = 15 pF;
VCC = 5 V
nCP to nQ, nQ15
17
ns
nSD to nQ, nQ12
14
ns
nRD to nQ, nQ12
15
ns
fmax
maximum clock frequency
75
61
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation
capacitance per ip-op
notes 1 and 2
20
22
pF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74HC109DB-T | 功能描述:觸發(fā)器 DUAL J-K W/NEG-EDGE TRIG RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74HC109D-Q100J | 功能描述:74HC109D-Q100/SOT109/SO16 制造商:nexperia usa inc. 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:2,500 |
| 74HC109D-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
| 74HC109E | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 74HC109N | 功能描述:觸發(fā)器 DUAL J-K W/NEG-EDGE TRIG RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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