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參數資料
| 型號： | 74HC109N,652 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 2/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DUAL JK F-F POS-EDGE 16DIP |
| 產品培訓模塊： | Logic Packages |
| 標準包裝： | 1,000 |
| 系列： | 74HC |
| 功能： | 設置（預設）和復位 |
| 類型： | JK 型 |
| 輸出類型： | 差分 |
| 元件數： | 2 |
| 每個元件的位元數： | 1 |
| 頻率 - 時鐘： | 81MHz |
| 延遲時間 - 傳輸： | 8ns |
| 觸發(fā)器類型： | 正邊沿 |
| 輸出電流高，低： | 5.2mA，5.2mA |
| 電源電壓： | 2 V ~ 6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 其它名稱： | 954-74HC109N,652CHP 954-74HC109N652CHP |
1997 Nov 25
2
Philips Semiconductors
Product specication
Dual JK ip-op with set and reset;
positive-edge trigger
74HC/HCT109
FEATURES
J, K inputs for easy D-type flip-flop
Toggle flip-flop or “do nothing” mode
Output capability: standard
ICC category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT109 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT109 are dual positive-edge triggered, JK
flip-flops with individual J, K inputs, clock (CP) inputs, set
(SD) and reset (RD) inputs; also complementary Q and Q
outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input.
The J and K inputs control the state changes of the
flip-flops as described in the mode select function table.
The J and K inputs must be stable one set-up time prior to
the LOW-to-HIGH clock transition for predictable
operation.
The JK design allows operation as a D-type flip-flop by
tying the J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CL = 15 pF;
VCC = 5 V
nCP to nQ, nQ15
17
ns
nSD to nQ, nQ12
14
ns
nRD to nQ, nQ12
15
ns
fmax
maximum clock frequency
75
61
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation
capacitance per ip-op
notes 1 and 2
20
22
pF
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 74HC109PW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual JK flip-flop with set and reset; positive-edge trigger |
| 74HC10D | 功能描述:邏輯門 TRIPLE 3-INPUT NAND GATE RoHS:否 制造商:Texas Instruments 產品:OR 邏輯系列:LVC 柵極數量:2 線路數量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| 74HC10D,652 | 功能描述:邏輯門 TRIPLE 3-INPUT NAND RoHS:否 制造商:Texas Instruments 產品:OR 邏輯系列:LVC 柵極數量:2 線路數量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| 74HC10D,653 | 功能描述:邏輯門 TRIPLE 3-INPUT NAND GATE RoHS:否 制造商:Texas Instruments 產品:OR 邏輯系列:LVC 柵極數量:2 線路數量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| 74HC10D,653-CUT TAPE | 制造商:NXP 功能描述:74HC10 Series 6 V High-Speed Si-Gate CMOS Triple 3-Input NAND Gate - SOIC-14 |
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