參數(shù)資料
型號(hào): 74HC160N,652
廠商: NXP Semiconductors
文件頁(yè)數(shù): 6/7頁(yè)
文件大小: 0K
描述: IC SYNC BCD DECADE COUNT 16DIP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 25
系列: 74HC
邏輯類型: 計(jì)數(shù)器,十進(jìn)制
方向:
元件數(shù): 1
每個(gè)元件的位元數(shù): 4
復(fù)位: 異步
計(jì)時(shí): 同步
計(jì)數(shù)速率: 66MHz
觸發(fā)器類型: 正邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 通孔
封裝/外殼: 16-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 16-DIP
包裝: 管件
其它名稱: 568-7797-5
74HC160N
74HC160N,652-ND
74HC160N-ND
933669360652
74HC73_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 19 March 2008
8 of 16
NXP Semiconductors
74HC73
Dual JK ip-op with reset; negative-edge trigger
11. Waveforms
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6.
Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the J
and K to nCP set-up and hold times, the output transition times and the maximum clock frequency
tsu
1/f max
th
nCP input
VM
th
tsu
tW
nJ, nK
input
001aab983
nQ output
VI
GND
90 %
10 %
90 %
VI
VOH
VOL
VOH
VOL
GND
nQ output
tPHL
tPLH
VM
tTLH
tTHL
tTLH
VM
tTHL
tPLH
tPHL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7.
Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays and the reset pulse width
and the nR to nCP removal time
001aab984
nQ output
VI
GND
VI
GND
VOH
VOL
VOH
VOL
tW
nR input
VM
nQ output
nCP input
VM
trec
tPHL
tPLH
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