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參數(shù)資料
| 型號(hào)： | 74HC162 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Presettable synchronous BCD decade counter; synchronous reset |
| 中文描述： | 可預(yù)置同步BCD碼十進(jìn)制計(jì)數(shù)器，同步復(fù)位 |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大小： | 83K |
| 代理商： | 74HC162 |
December 1990
7
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
counter; synchronous reset
74HC/HCT162
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
°
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+
25
40 to
+
85
40 to
+
125
min.
typ.
max.
min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
58
21
17
69
25
20
39
14
11
19
7
6
22
8
6
28
10
8
39
14
11
69
25
20
17
6
5
19
57
68
190
38
32
215
43
37
150
30
26
75
15
13
240
48
41
270
54
46
190
38
33
95
19
16
285
57
48
325
65
55
225
45
38
110
22
19
ns
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.8
t
PHL
/ t
PLH
propagation delay
CP to TC
ns
Fig.8
t
PHL
/ t
PLH
propagation delay
CET to TC
ns
Fig.9
t
THL
/ t
TLH
output transition
time
ns
Figs 8 and 9
t
W
clock pulse width
HIGH or LOW
80
16
14
100
20
17
135
27
23
200
40
34
0
0
0
6.0
30
35
100
20
17
125
25
21
170
34
29
250
50
43
0
0
0
4.8
24
28
120
24
20
150
30
26
205
41
35
300
60
51
0
0
0
4.0
20
24
ns
Fig.8
t
su
set-up time
MR, D
n
to CP
ns
Figs 9 and 11
t
su
set-up time
PE to CP
ns
Fig.9
t
su
set-up time
CEP, CET to CP
ns
Fig.12
t
h
hold time
D
n
, PE, CEP,
CET, MR to CP
maximum clock
pulse
frequency
ns
Figs 9, 11 and
12
f
max
MHz
Fig.8
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