參數(shù)資料
型號： 74HC181N
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： 4-bit arithmetic logic unit
中文描述： HC/UH SERIES, 4-BIT ARITHMETIC LOGIC UNIT, PDIP24
封裝： 0.600 INCH, PLASTIC, SOT-101-1, DIP-24
文件頁數(shù)： 7/20頁
文件大?。?/td> 165K
代理商： 74HC181N
1998 Jun 10
7
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
74HC/HCT181
Table 1
SUM MODE TEST
Function inputs S
0
= S
3
= 4.5 V, M = S
1
= S
2
= 0 V
Table 2
DIFFERENTIAL MODE TEST
Function inputs S
1
= S
2
= 4.5 V, M = S
0
= S
3
= 0 V
Table 3
LOGIC MODE TEST
Function inputs M = S
1
= S
2
= 4.5 V, S
0
= S
3
= 0 V
PARAMETER
INPUT
UNDER
TEST
OTHER INPUT, SAME BIT
OTHER DATA INPUTS
OUTPUT
UNDER
TEST
Apply 4.5 V
Apply GND
Apply 4.5 V
Apply GND
t
PLH
/ t
PHL
t
PLH
/ t
PHL
t
PLH
/ t
PHL
t
PLH
/ t
PHL
t
PLH
/ t
PHL
t
PLH
/ t
PHL
t
PLH
/ t
PHL
t
PLH
/ t
PHL
t
PLH
/ t
PHL
A
i
B
i
A
i
B
i
A
i
B
i
A
i
B
i
C
n
B
i
A
i
B
i
A
i
none
none
none
none
none
none
none
none
none
B
i
A
i
B
i
A
i
none
remaining A and B
remaining A and B
none
none
remaining B
remaining B
remaining B
remaining B
all A
C
n
C
n
remaining A and B, C
n
remaining A and B, C
n
remaining A, C
n
remaining A, C
n
remaining A, C
n
remaining A, C
n
all B
F
i
F
i
P
P
G
G
C
n+4
C
n+4
any F or C
n+4
PARAMETER
INPUT
UNDER
TEST
OTHER INPUT, SAME BIT
OTHER DATA INPUTS
OUTPUT
UNDER
TEST
Apply 4.5 V
Apply GND
Apply 4.5 V
Apply GND
t
PLH
/ t
PHL
t
PLH
/ t
PHL
t
PLH
/ t
PHL
t
PLH
/ t
PHL
t
PLH
/ t
PHL
t
PLH
/ t
PHL
t
PLZ
/ t
PZL
t
PLZ
/ t
PZL
t
PLH
/ t
PHL
t
PLH
/ t
PHL
t
PLH
/ t
PHL
A
i
B
i
A
i
B
i
A
i
B
i
A
i
B
i
A
i
B
i
C
n
none
A
i
none
A
i
B
i
none
none
A
i
B
i
none
none
B
i
none
B
i
none
none
A
i
B
i
none
none
A
i
none
remaining A
remaining A
none
none
none
none
remaining A
remaining A
none
none
all A and B
remaining B, C
n
remaining B, C
n
remaining A and B, C
n
remaining A and B, C
n
remaining A and B, C
n
remaining A and B, C
n
remaining B, C
n
remaining B, C
n
remaining A and B, C
n
remaining A and B, C
n
none
F
i
F
i
P
P
G
G
A=B
A=B
C
n+4
C
n+4
any F or C
n+4
PARAMETER
INPUT
UNDER
TEST
OTHER INPUT, SAME BIT
OTHER DATA INPUTS
OUTPUT
UNDER
TEST
Apply 4.5 V
Apply GND
Apply 4.5 V
Apply GND
t
PLH
/ t
PHL
t
PLH
/ t
PHL
A
i
B
i
B
i
A
i
none
none
none
none
remaining A and B, C
n
remaining A and B, C
n
F
i
F
i
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