參數資料
型號: 74HC191DB,118
廠商: NXP Semiconductors
文件頁數: 3/14頁
文件大小: 0K
描述: IC 4BIT BINAR UP/DN COUNT 16SSOP
產品培訓模塊: Logic Packages
標準包裝: 2,000
系列: 74HC
邏輯類型: 二進制計數器
方向: 上,下
元件數: 1
每個元件的位元數: 4
計時: 同步
計數速率: 39MHz
觸發(fā)器類型: 正邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 16-SSOP
包裝: 帶卷 (TR)
其它名稱: 74HC191DB-T
74HC191DB-T-ND
935188600118
December 1990
11
Philips Semiconductors
Product specication
Presettable synchronous 4-bit binary
up/down counter
74HC/HCT191
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC
VCC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max. min.
max.
tPHL/ tPLH
propagation delay
CP to Qn
26
48
60
72
ns
4.5
Fig.10
tPHL/ tPLH
propagation delay
CP to TC
32
51
64
77
ns
4.5
Fig.10
tPHL/ tPLH
propagation delay
CP to RC
19
35
44
53
ns
4.5
Fig.11
tPHL/ tPLH
propagation delay
CE to RC
19
33
41
50
ns
4.5
Fig.11
tPHL/ tPLH
propagation delay
Dn to Qn
22
44
55
66
ns
4.5
Fig.12
tPHL/ tPLH
propagation delay
PL to Qn
27
46
58
69
ns
4.5
Fig.13
tPHL/ tPLH
propagation delay
U/D to TC
23
45
56
68
ns
4.5
Fig.14
tPHL/ tPLH
propagation delay
U/D to RC
24
45
56
68
ns
4.5
Fig.14
tTHL/ tTLH
output transition time
7
15
19
22
ns
4.5
Fig.15
tW
clock pulse width
HIGH or LOW
16
9
20
24
ns
4.5
Fig.10
tW
parallel load pulse width
LOW
22
11
28
33
ns
4.5
Fig.15
trem
removal time
PL to CP
7
1
9
11
ns
4.5
Fig.15
tsu
set-up time
U/D to CP
41
20
51
62
ns
4.5
Fig.17
tsu
set-up time
Dn to PL
20
9
25
30
ns
4.5
Fig.16
tsu
set-up time
CE to CP
30
18
38
45
ns
4.5
Fig.17
th
hold time
U/D to CP
0
18
0
ns
4.5
Fig.17
th
hold time
Dn to PL
0
5
0
ns
4.5
Fig.16
th
hold time
CE to CP
0
10
0
ns
4.5
Fig.17
fmax
maximum clock pulse
frequency
20
33
16
13
MHz
4.5
Fig.10
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