參數(shù)資料
型號: 74HC193PW,118
廠商: NXP Semiconductors
文件頁數(shù): 9/30頁
文件大?。?/td> 0K
描述: IC 4BIT BINARY UP/DN CNT 16TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,500
系列: 74HC
邏輯類型: 二進(jìn)制計數(shù)器
方向: 上,下
元件數(shù): 1
每個元件的位元數(shù): 4
復(fù)位: 異步
計時: 同步
計數(shù)速率: 49MHz
觸發(fā)器類型: 正邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
其它名稱: 74HC193PW-T
74HC193PW-T-ND
935188980118
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
17 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
[1]
tpd is the same as tPHL and tPLH.
[2]
CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD VCC2 fi N+ (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(C
L VCC
2
f
o) = sum of outputs.
trec
recovery time
PL to CPU, CPD;
VCC =4.5 V
10
2
-
13
-
15
-
ns
MR to CPU, CPD;
VCC =4.5 V
10
0
-
13
-
15
-
ns
tsu
set-up time
Dn to PL; see
Figure 13; note:
CPU = CPD =
HIGH
VCC =4.5 V
16
8
-
20
-
24
-
ns
th
hold time
Dn to PL; see
VCC =4.5 V
0
6-
0
-
0
-
ns
CPU to CPD,
CPD to CPU; see
VCC =4.5 V
16
7
-
20
-
24
-
ns
fmax
maximum
frequency
CPU, CPD; see
VCC =4.5 V
20
43
-
16
-
13
-
MHz
CPD
power
dissipation
capacitance
VI = GND to VCC
1.5 V; VCC =5V;
fi =1 MHz
-26-
-
pF
Table 9.
Dynamic characteristics type 74HCT193 …continued
Symbol
Parameter
Conditions
25
C
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
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