參數(shù)資料
型號(hào): 74HC40103DB,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 7/25頁(yè)
文件大?。?/td> 0K
描述: IC 8BIT SYNC BINARY DOWN 16-SSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 78
系列: 74HC
邏輯類型: 二進(jìn)制計(jì)數(shù)器
方向:
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
復(fù)位: 異步
計(jì)時(shí): 同步
計(jì)數(shù)速率: 32MHz
觸發(fā)器類型: 正邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 管件
其它名稱: 568-2677-5
935189340112
9397 750 13812
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
15 of 25
Philips Semiconductors
74HC40103
8-bit synchronous binary down counter
[1]
CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(C
L × VCC
2
× f
o) = sum of outputs.
tsu
set-up time PE to CP
VCC = 2.0 V
110
-
ns
VCC = 4.5 V
22
-
ns
VCC = 6.0 V
19
-
ns
set-up time TE to CP
VCC = 2.0 V
225
-
ns
VCC = 4.5 V
45
-
ns
VCC = 6.0 V
38
-
ns
set-up time Pn to CP
VCC = 2.0 V
110
-
ns
VCC = 4.5 V
22
-
ns
VCC = 6.0 V
19
-
ns
th
hold time PE to CP
VCC = 2.0 V
0
-
ns
VCC = 4.5 V
0
-
ns
VCC = 6.0 V
0
-
ns
hold time TE to CP
VCC = 2.0 V
0
-
ns
VCC = 4.5 V
0
-
ns
VCC = 6.0 V
0
-
ns
hold time Pn to CP
VCC = 2.0 V
0
-
ns
VCC = 4.5 V
0
-
ns
VCC = 6.0 V
0
-
ns
fmax
maximum clock frequency
VCC = 2.0 V
2.0
-
MHz
VCC = 4.5 V
10
-
MHz
VCC = 6.0 V
12
-
MHz
Table 8:
Dynamic characteristics …continued
GND = 0 V; tr =tf = 6 ns; CL = 50 pF; see Figure 13.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
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