參數(shù)資料
型號: 74HC4017DB,118
廠商: NXP Semiconductors
文件頁數(shù): 7/24頁
文件大小: 0K
描述: IC JOHNSON DECADE COUNTER 16SSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標準包裝: 2,000
系列: 74HC
邏輯類型: 計數(shù)器,十進制
方向:
元件數(shù): 1
每個元件的位元數(shù): 10
復(fù)位: 異步
計數(shù)速率: 83MHz
觸發(fā)器類型: 正邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 帶卷 (TR)
其它名稱: 74HC4017DB-T
74HC4017DB-T-ND
935189360118
74HC_HCT4017
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 10 December 2013
15 of 24
NXP Semiconductors
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
Remark: It is essential not to enable the counter on CP1 when CP0 is HIGH, or on CP0
when CP1 is LOW, as this would cause an extra count.
Figure 13 shows an example of a divide-by 2 through divide-by 10 circuit using one
74HC4017; 74HCT4017. Since the 74HC4017; 74HCT4017 has an asynchronous reset,
the output pulse widths are narrow (minimum expected pulse width is 6 ns). The output
pulse widths can be enlarged by inserting an RC network at the MR input.
Fig 12. Counter expansion
Fig 13. Divide-by 2 through divide-by 10
001aah248
8 decoded
outputs
8 decoded
outputs
CP0
CP1
Q0 Q1
Q8 Q9
74HC4017
74HCT4017
74HC4017
74HCT4017
74HC4017
74HCT4017
- - - -
CP0
CP1
Q0 Q1
Q8 Q9
- - - -
CP0
CP1
Q1
Q8 Q9
- - - - - -
MR
clock
first stage
last stage
intermediate stages
MR
9 decoded
outputs
Q4
Q8
GND
divide - by 4
divide - by 8
Q9
divide - by 9
Q3
divide - by 3
Q7
divide - by 7
Q6
divide - by 6
Q2
divide - by 2
Q0
Q1
Q5
divide - by 5
Q5-9
divide - by 10
CP1
CP0
fin
fout
MR
VCC
001aah249
74HC4017
74HCT4017
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