參數(shù)資料
型號: 74HC4020DB,112
廠商: NXP Semiconductors
文件頁數(shù): 6/7頁
文件大?。?/td> 0K
描述: IC 14-STAGE BINARY RIPPLE 16SSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標準包裝: 78
系列: 74HC
邏輯類型: 二進制計數(shù)器
方向:
元件數(shù): 1
每個元件的位元數(shù): 14
復(fù)位: 異步
計數(shù)速率: 109MHz
觸發(fā)器類型: 負邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 管件
產(chǎn)品目錄頁面: 834 (CN2011-ZH PDF)
其它名稱: 568-2685-5
935188720112
1998 Jul 08
6
Philips Semiconductors
Product specication
Hex D-type ip-op with reset; positive-edge trigger
74HC/HCT174
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (
I
CC) for a unit load of 1 is given in the family specifications.
To determine
ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
INPUT
UNIT LOAD COEFFICIENT
Dn
0.25
CP
1.30
MR
1.25
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
WAVEFORMS
+25
40 to +85 40 to +125
min.
typ.
max. min. max.
min.
max.
tPHL/ tPLH
propagation delay
CP to Qn
21
35
44
53
ns
4.5
Fig.6
tPHL
propagation delay
MR to Qn
20
35
44
53
ns
4.5
Fig.7
tTHL/ tTLH
output transition time
7
15
19
22
ns
4.5
Fig.6
tW
clock pulse width
HIGH or LOW
16
7
20
24
ns
4.5
Fig.6
tW
master reset pulse
width; LOW
20
7
25
30
ns
4.5
Fig.7
trem
removal time MR to CP
12
3
15
18
ns
4.5
Fig.7
tsu
set-up time Dn to CP
16
4
20
24
ns
4.5
Fig.8
th
hold time Dn to CP
5
3
5
ns
4.5
Fig.8
fmax
maximum clock pulse
frequency
30
63
24
20
MHz
4.5
Fig.6
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