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參數(shù)資料
型號(hào): 74HC4059D,118
廠(chǎng)商: NXP Semiconductors
文件頁(yè)數(shù): 15/20頁(yè)
文件大?。?/td> 0K
描述: IC PROG DIV-BY-N COUNTER 24SOIC
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 1
系列: 74HC
邏輯類(lèi)型: 除以 N
方向:
元件數(shù): 1
每個(gè)元件的位元數(shù): 16
復(fù)位: 異步
計(jì)時(shí): 同步
計(jì)數(shù)速率: 43MHz
觸發(fā)器類(lèi)型: 正邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SO
包裝: 標(biāo)準(zhǔn)包裝
其它名稱(chēng): 568-8152-6
1998 Jul 08
4
Philips Semiconductors
Product specication
Programmable divide-by-n counter
74HC/HCT4059
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay CP to Q
CL = 15 pF; VCC = 5 V 1820ns
fmax
maximum clock frequency
40
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per package
notes 1 and 2
30
32
pF
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
74HC4059N3;
74HCT4059N3
DIP24
plastic dual in-line package; 24 leads (300 mil)
SOT222-1
74HC4059N;
74HCT4059N
DIP24
plastic dual in-line package; 24 leads (600 mil)
SOT101-1
74HC4059D;
74HCT4059D
SO24
plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
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