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參數(shù)資料
| 型號(hào)： | 74HC4515PW |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-to-16 line decoder/demultiplexer with input latches; inverting |
| 中文描述： | HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO24 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 64K |
| 代理商： | 74HC4515PW |
September 1993
2
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer with
input latches; inverting
74HC/HCT4515
FEATURES
Inverting outputs
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4515 are high-speed Si-gate CMOS
devices and are pin compatible with “4515” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4515 are 4-to-16 line
decoders/demultiplexers having four binary weighted
address inputs (A
0
to A
3
) with latches, a latch enable input
(LE), and an active LOW enable input (E). The 16 inverting
outputs (Q
0
to Q
15
) are mutually exclusive active LOW.
When LE is HIGH, the selected output is determined by the
data on A
n
. When LE goes LOW, the last data present at
A
n
are stored in the latches and the outputs remain stable.
When E is LOW, the selected output, determined by the
contents of the latch, is LOW. When E is HIGH, all outputs
are HIGH. The enable input (E) does not affect the state of
the latch.
When the “4515” is used as a demultiplexer, E is the data
input and A
0
to A
3
are the address inputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
C
I
C
PD
propagation delay A
n
to Q
n
input capacitance
power dissipation capacitance per package
C
L
= 15 pF; V
CC
= 5 V
25
3.5
44
26
3.5
46
ns
pF
pF
notes 1 and 2
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