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參數(shù)資料
| 型號(hào)： | 74HC533 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal D-type transparent latch; 3-state; inverting |
| 中文描述： | 八路D型透明鎖存器，三態(tài);反相 |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大?。?/td> | 62K |
| 代理商： | 74HC533 |
December 1990
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
74HC/HCT533
FEATURES
3-state inverting outputs for bus oriented applications
Common 3-state output enable input
Output capability: bus driver
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT533 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT533 are octal D-type transparent latches
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all
latches.
The “533” consists of eight D-type transparent latches with
3-state inverting outputs. When LE is HIGH, data at the D
n
inputs enter the latches. In this condition the latches are
transparent, i.e. a latch output will change state each time
its corresponding D-input changes.
When LE is LOW the latches store the information that was
present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the 8 latches are
available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The “533” is functionally identical to the “373”, “563” and
“573”, but the “373” and “573” have non-inverted outputs
and the “563” and “573” have a different pin arrangement.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL/
t
PLH
propagation delay
D
n
to Q
n
LE to Q
n
input capacitance
power dissipation capacitance per latch
C
L
= 15 pF; V
CC
= 5 V
14
18
3.5
34
16
19
3.5
34
ns
ns
pF
pF
C
I
C
PD
notes 1 and 2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74HC534N,652 | 制造商:NXP Semiconductors 功能描述: |
| 74HC540A | 制造商:Toshiba America Electronic Components 功能描述: |
| 74HC540D | 功能描述:緩沖器和線路驅(qū)動(dòng)器 OCT BUF/DRVR INV 3ST RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| 74HC540D(BJ) | 功能描述:Buffer, Inverting 1 Element 8 Bit per Element Push-Pull Output 20-SOIC 制造商:toshiba semiconductor and storage 系列:74HC 包裝:剪切帶（CT） 零件狀態(tài):在售 邏輯類型:緩沖器，反向 元件數(shù):1 每元件位數(shù):8 輸入類型:- 輸出類型:推挽式 電流 - 輸出高，低:7.8mA，7.8mA 電壓 - 電源:2 V ~ 6 V 工作溫度:-40°C ~ 85°C（TA） 安裝類型:表面貼裝 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 供應(yīng)商器件封裝:20-SOIC 標(biāo)準(zhǔn)包裝:1 |
| 74HC540D,652 | 功能描述:緩沖器和線路驅(qū)動(dòng)器 OCT BUF/DRVR INV 3ST RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
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