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參數(shù)資料
| 型號： | 74HC74PW,118 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 20/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DUAL POS-EDG-TRG D FF 14TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 74HC |
| 功能： | 設(shè)置（預(yù)設(shè)）和復(fù)位 |
| 類型： | D 型 |
| 輸出類型： | 差分 |
| 元件數(shù)： | 2 |
| 每個元件的位元數(shù)： | 1 |
| 頻率 - 時鐘： | 82MHz |
| 延遲時間 - 傳輸： | 14ns |
| 觸發(fā)器類型： | 正邊沿 |
| 輸出電流高，低： | 5.2mA，5.2mA |
| 電源電壓： | 2 V ~ 6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 832 (CN2011-ZH PDF) |
| 其它名稱： | 568-4574-6 |
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
8 of 21
NXP Semiconductors
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
tsu
set-up time
nD to nCP; see Figure 7
VCC = 2.0 V
75
6
-
90
-
ns
VCC = 4.5 V
15
2
-
18
-
ns
VCC = 6.0 V
13
2
-
15
-
ns
th
hold time
nD to nCP; see Figure 7
VCC = 2.0 V
3
6-
3
-
ns
VCC = 4.5 V
3
2-
3
-
ns
VCC = 6.0 V
3
2-
3
-
ns
fmax
maximum
frequency
nCP; see Figure 7
VCC = 2.0 V
4.8
23
-
4.0
-
MHz
VCC = 4.5 V
24
69
-
20
-
MHz
VCC =5V; CL =15pF
-
76
-
MHz
VCC = 6.0 V
28
82
-
24
-
MHz
CPD
power
dissipation
capacitance
CL =50pF;f= 1 MHz;
VI =GND to VCC
-24
-
pF
74HCT74
tpd
propagation
delay
nCP to nQ, nQ; see
VCC = 4.5 V
-
18
44
-
53
ns
VCC =5V; CL =15pF
-
15
-
ns
nSD to nQ, nQ; see
VCC = 4.5 V
-
23
50
-
60
ns
VCC =5V; CL =15pF
-
18
-
ns
nRD to nQ, nQ; see
VCC = 4.5 V
-
24
50
-
60
ns
VCC =5V; CL =15pF
-
18
-
ns
tt
transition
time
nQ, nQ; see Figure 7
VCC = 4.5 V
-
7
19
-
22
ns
tW
pulse width
nCP HIGH or LOW;
see Figure 7
VCC = 4.5 V
23
9
-
27
-
ns
nSD, nRD LOW;
see Figure 8
VCC = 4.5 V
20
9
-
24
-
ns
trec
recovery
time
nSD, nRD; see Figure 8
VCC = 4.5 V
8
1
-
9
-
ns
tsu
set-up time
nD to nCP; see Figure 7
VCC = 4.5 V
15
5
-
18
-
ns
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter
Conditions
Tamb = 40 C to +85 C
Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
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