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參數(shù)資料
| 型號(hào)： | 74HCT162 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Quadruple 2-Line To 1-Line Data Selectors/Multiplexers 16-SOIC -40 to 85 |
| 中文描述： | 可預(yù)置同步BCD碼十進(jìn)制計(jì)數(shù)器，同步復(fù)位 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大小： | 83K |
| 代理商： | 74HCT162 |
December 1990
2
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
counter; synchronous reset
74HC/HCT162
FEATURES
Synchronous counting and loading
Two count enable inputs for n-bit cascading
Positive-edge triggered clock
Synchronous reset
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT162 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT162 are synchronous presettable decade
counters which feature an internal look-ahead carry and
can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the
clock (CP).
The outputs (Q
0
to Q
3
) of the counters may be preset to a
HIGH or LOW level. A LOW level at the parallel enable
input (PE) disables the counting action and causes the
data at the data inputs (D
0
to D
3
) to be loaded into the
counter on the positive-going edge of the clock (providing
that the set-up and hold time requirements forPE are met).
Preset takes place regardless of the levels at count enable
inputs (CEP and CET).
For the “162” the clear function is synchronous.
A LOW level at the master reset input (MR) sets all four
outputs of the flip-flops (Q
0
to Q
3
) to LOW level after the
next positive-going transition on the clock (CP) input
(provided that the set-up and hold time requirements for
MR are met). This action occurs regardless of the levels at
PE, CET and CEP inputs.
This synchronous reset feature enables the designer to
modify the maximum count with only one external NAND
gate.
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (CEP and CET) must
be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus
enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH level output of Q
0
. This
pulse can be used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:
f
max
=
)
t
P max
)
CP to TC
(
t
SU
(CEP to CP)
+
-------------------------------------------------1
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
propagation delay
CP to Q
n
CP to TC
CET to TC
propagation delay
CP to Q
n
CP to TC
CET to TC
maximum clock
frequency
input capacitance
power dissipation
capacitance per package
C
L
= 15 pF;
V
CC
= 5 V
19
21
11
20
26
15
ns
ns
ns
t
PLH
19
21
11
63
20
19
10
32
ns
ns
ns
MHz
f
max
C
I
C
PD
3.5
37
3.5
37
pF
pF
notes 1 and 2
Notes
1.
C
PD
is used to determine the
dynamic power dissipation
(P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
)
where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of
outputs
C
L
= output load capacitance in
pF
V
CC
= supply voltage in V
For HC the condition is
V
I
= GND to V
CC
For HCT the condition is
V
I
= GND to V
CC
1.5 V
2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74HC162 | Presettable synchronous BCD decade counter; synchronous reset |
| 74HCT163 | Presettable synchronous 4-bit binary counter; asynchronous reset(可預(yù)置的同步4位二進(jìn)制計(jì)數(shù)器；異步復(fù)位；) |
| 74HC163 | Presettable synchronous 4-bit binary counter; synchronous reset |
| 74HCT164 | 8-bit serial-in/parallel-out shift register(8位串入并出移位寄存器) |
| 74HCT166 | 8-bit parallel-in/serial-out shift register(8位并入/串出移位寄存器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74HCT163 | 制造商:NTE Electronics 功能描述: |
| 74HCT163D | 功能描述:計(jì)數(shù)器 IC SYNC 4-BIT BINARY COUNTER RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| 74HCT163D,652 | 功能描述:計(jì)數(shù)器 IC SYNC 4-BIT BINARY RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| 74HCT163D,653 | 功能描述:計(jì)數(shù)器移位寄存器 SYNC 4-BIT BINARY RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| 74HCT163D653 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
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