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參數資料
| 型號： | 74HCT4017N,652 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 3/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC JOHNSON DECADE COUNTER 16-DIP |
| 產品培訓模塊： | Logic Packages |
| 標準包裝： | 1,000 |
| 系列： | 74HCT |
| 邏輯類型： | 計數器，十進制 |
| 方向： | 上 |
| 元件數： | 1 |
| 每個元件的位元數： | 10 |
| 復位： | 異步 |
| 計數速率： | 67MHz |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 16-DIP |
| 包裝： | 管件 |
74HC_HCT4017
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 10 December 2013
11 of 24
NXP Semiconductors
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
[1]
tpd is the same as tPHL and tPLH.
[2]
tt is the same as tTHL and tTLH.
[3]
CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD VCC2 fi N+ (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(C
L VCC
2
f
o) = sum of outputs.
tt
transition time
see Figure 10
VCC = 4.5 V
-
7
15
-
19
-
22
ns
tW
pulse width
CP0 and CP1 (HIGH or
LOW); see Figure 9
VCC = 4.5 V
16
7
-
20
-
24
-
ns
MR (HIGH); see Figure 9
VCC = 4.5 V
16
4
-
20
-
24
-
ns
tsu
set-up time
CP1toCP0; CP0 to CP1;
see Figure 8
VCC = 4.5 V
10
3
-
13
-
15
-
ns
th
hold time
CP1toCP0; CP0 to CP1;
see Figure 8
VCC = 4.5 V
10
6
-
13
-
15
-
ns
trec
recovery time
MR to CP0 and
MR to CP1; see Figure 9
VCC = 4.5 V
5
5-
5
-
5
-
ns
fmax
maximum
frequency
CP0 or CP1; see Figure 9
VCC = 4.5 V
30
61
-
24
-
20
-
MHz
VCC = 5.0 V;
CL =15pF
-67
-
MHz
CPD
power
dissipation
capacitance
VI = GND to VCC 1.5 V;
VCC =5V; fi =1MHz
-36
-
pF
Table 7.
Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 11.
Symbol Parameter
Conditions
25
C
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
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