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參數(shù)資料
| 型號： | 74HCT4020N,652 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 14STAGE BINARY RIPPLE 16-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 系列： | 74HCT |
| 邏輯類型： | 二進制計數(shù)器 |
| 方向： | 上 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 14 |
| 復(fù)位： | 異步 |
| 計數(shù)速率： | 47MHz |
| 觸發(fā)器類型： | 負(fù)邊沿 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 16-DIP |
| 包裝： | 管件 |
| 其它名稱： | 568-7849-5 74HCT4020N 74HCT4020N,652-ND 74HCT4020N-ND 933670320652 |
September 1993
2
Philips Semiconductors
Product specication
14-stage binary ripple counter
74HC/HCT4020
FEATURES
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4020 are high-speed Si-gate CMOS
devices and are pin compatible with the “4020” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4020 are 14-stage binary ripple counters
with a clock input (CP), an overriding asynchronous
master reset input (MR) and twelve fully buffered parallel
outputs (Q0, Q3 to Q13).
The counter is advanced on the HIGH-to-LOW transition of
CP.
A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CL = 15 pF; VCC =5 V
CP to Q0
11
15
ns
Qn to Qn+1
66ns
MR to Qn
17
19
ns
fmax
maximum clock frequency
101
52
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per package
notes 1 and 2
19
20
pF
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