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參數(shù)資料
型號(hào): 74HCT4059D,118
廠商: NXP Semiconductors
文件頁數(shù): 18/20頁
文件大?。?/td> 0K
描述: IC PROG DIVIDE-BY-N COUNT 24SOIC
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 1,000
系列: 74HCT
邏輯類型: 除以 N
方向:
元件數(shù): 1
每個(gè)元件的位元數(shù): 16
復(fù)位: 異步
計(jì)時(shí): 同步
計(jì)數(shù)速率: 36MHz
觸發(fā)器類型: 正邊沿
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SO
包裝: 帶卷 (TR)
其它名稱: 74HCT4059D-T
74HCT4059D-T-ND
933757430118
1998 Jul 08
7
Philips Semiconductors
Product specication
Programmable divide-by-n counter
74HC/HCT4059
FUNCTION TABLE
Note
1. It is recommended that the device is in the master preset mode (Kb =Kc = logic 0) in order to correctly initialize the
device prior to start-up. An example of a suitable external circuit is shown in Fig.14.
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Table 1
Table 2
Table 3
LATCH
ENABLE
INPUT
MODE
SELECT
INPUTS
FIRST COUNTING
SECTION
DECADE 1
LAST COUNTING
SECTION
DECADE 5
COUNTER
RANGE
OPERATION
LE
Ka Kb Kc MODE
MAX
PRESET
STATE
JAM
INPUTS
USED
DIVIDED
BY
MAX.
PRESET
STATE
JAM
INPUTS
USED
BCD
MAX.
BINARY
MAX.
HH
H
2
1
J1
87
J2J3J4
15 999 17 331
timer mode
HL
H
4
3
J1J2
43
J3J4
15 999 18 663
HH
L
H
5
4
J1J2J3
21
J4
9 999 13 329
HL
L
H
8
7
J1J2J3
21
J4
15 999 21 327
HH
H
L
10
9
J1J2J3J4 10
9 999 16 659
LH
H
2
1
J1
87
J2J3J4
15 999 17 331
divide-by-n mode
LL
H
4
3
J1J2
43
J3J4
15 999 18 663
LH
L
H
5
4
J1J2J3
21
J4
9 999 13 329
LL
L
H
8
7
J1J2J3
21
J4
15 999 21 327
LH
H
L
10
9
J1J2J3J4 10
9 999 16 659
HL
H
L
10
9
J1J2J3J4 10
9 999 16 659
L
H
L
preset inhibited
xed
10 000
divide-by-10 000
mode
X
L
master preset
master preset
mode
41
5
9
6
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
LL
H
L
H
L
H
L
H
L
H
L
61
7
4
5
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
L
H
HH
H
L
HL
H
L
H
L
97
4
8
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
H
L
H
HH
H
L
HL
L
H
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