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參數(shù)資料
| 型號： | 74HCT4516 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-Bit Synchronous Up/Down Binary Counters 16-SOIC -40 to 85 |
| 中文描述： | 二進制向上/向下計數(shù)器 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 100K |
| 代理商： | 74HCT4516 |
December 1990
2
Philips Semiconductors
Product specification
Binary up/down counter
74HC/HCT4516
FEATURES
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4516 are high-speed Si-gate CMOS
devices and are pin compatible with the “4516” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4516 are edge-triggered synchronous
up/down 4-bit binary counters with a clock input (CP), an
up/down count control input (UP/DN), an active LOW
count enable input (CE), an asynchronous active HIGH
parallel load input (PL), four parallel inputs (D
0
to D
3
), four
parallel outputs (Q
0
to Q
3
), an active LOW terminal count
output (TC), and an overriding asynchronous master reset
input (MR).
Information on D
0
to D
3
is loaded into the counter while PL
is HIGH, independent of all other input conditions except
the MR input, which must be LOW. When PL and CE are
LOW, the counter changes on the LOW-to-HIGH transition
of CP. UP/DN determines the direction of the count, HIGH
for counting up, LOW for counting down. When counting
up, TC is LOW when Q
0
to Q
3
are HIGH and CE is LOW.
When counting down, TC is LOW when Q
0
to Q
3
and CE
are LOW. A HIGH on MR resets the counter (Q
0
to
Q
3
= LOW) independent of all other input conditions.
Logic equation for terminal count:
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
f
max
C
I
C
PD
propagation delay CP to Q
n
maximum clock frequency
input capacitance
power dissipation capacitance per package
C
L
= 15 pF; V
CC
= 5 V
19
45
3.5
59
19
57
3.5
61
ns
MHz
pF
pF
notes 1 and 2
TC = CE . {(UP/DN) . Q
0
. Q
1
. Q
2
. Q
3
+ (UP DN
) . Q
0
. Q
1
. Q
2
. Q
3
}
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