參數(shù)資料
型號: 74HCT74PW,118
廠商: NXP Semiconductors
文件頁數(shù): 16/21頁
文件大小: 0K
描述: IC DUAL D FF POSEDG TRIG 14TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 1
系列: 74HCT
功能: 設(shè)置(預(yù)設(shè))和復(fù)位
類型: D 型
輸出類型: 差分
元件數(shù): 2
每個(gè)元件的位元數(shù): 1
頻率 - 時(shí)鐘: 18MHz
延遲時(shí)間 - 傳輸: 18ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 4mA,4mA
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 836 (CN2011-ZH PDF)
其它名稱: 568-4595-6
74HC_HCT74
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
4 of 21
NXP Semiconductors
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
6.
Functional description
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
[1]
H = HIGH voltage level; L = LOW voltage level;
= LOW-to-HIGH transition; Q
n+1 = state after the next LOW-to-HIGH CP transition;
X = don’t care.
7.
Limiting values
[1]
For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
Table 3.
Function table[1]
Input
Output
nSD
nRD
nCP
nD
nQ
L
H
XXH
L
H
L
XXL
H
L
XXH
H
Table 4.
Function table[1]
Input
Output
nSD
nRD
nCP
nD
nQn+1
HH
LLH
HH
HHL
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
0.5
+7
V
IIK
input clamping current
VI < 0.5 V or VI >VCC +0.5 V
-
20
mA
IOK
output clamping current
VO < 0.5 V or VO >VCC +0.5 V
-
20
mA
IO
output current
VO = 0.5 V to (VCC +0.5 V)
-
25
mA
ICC
supply current
-
+100
mA
IGND
ground current
100
-
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
DIP14 package
750
mW
SO14, (T)SSOP14 and DHVQFN14
packages
500
mW
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