參數(shù)資料
型號(hào)： 74HCT93N,112
廠(chǎng)商： NXP Semiconductors
文件頁(yè)數(shù)： 2/7頁(yè)
文件大?。?/td> 0K
描述： IC 4BIT BIN RIPPLE COUNT 14DIP
產(chǎn)品培訓(xùn)模塊： Logic Packages
標(biāo)準(zhǔn)包裝： 25
系列： 74HCT
邏輯類(lèi)型： 二進(jìn)制計(jì)數(shù)器
方向： 上
元件數(shù)： 1
每個(gè)元件的位元數(shù)： 4
復(fù)位： 異步
計(jì)數(shù)速率： 70MHz
觸發(fā)器類(lèi)型： 負(fù)邊沿
電源電壓： 4.5 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 通孔
封裝/外殼： 14-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 14-DIP
包裝： 管件
其它名稱(chēng)： 74HCT93N
74HCT93N-ND
933756960112
December 1990
2
Philips Semiconductors
Product specication
4-bit binary ripple counter
74HC/HCT93
FEATURES
Various counting modes
Asynchronous master reset
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT93 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
no. 7A.
The 74HC/HCT93 are 4-bit binary
ripple counters. The devices consist
of four master-slave flip-flops
internally connected to provide a
divide-by-two section and a
divide-by-eight section. Each section
has a separate clock input (CP0 and
CP1) to initiate state changes of the
counter on the HIGH-to-LOW clock
transition. State changes of the Qn
outputs do not occur simultaneously
because of internal ripple delays.
Therefore, decoded output signals
are subject to decoding spikes and
should not be used for clocks or
strobes.
A gated AND asynchronous master
reset (MR1 and MR2) is provided
which overrides both clocks and
resets (clears) all flip-flops.
Since the output from the
divide-by-two section is not internally
connected to the succeeding stages,
the device may be operated in various
counting modes. In a 4-bit ripple
counter the output Q0 must be
connected externally to input CP1.
The input count pulses are applied to
clock input CP0. Simultaneous
frequency divisions of 2, 4, 8 and 16
are performed at the Q0, Q1, Q2 and
Q3 outputs as shown in the function
table. As a 3-bit ripple counter the
input count pulses are applied to input
CP1.
Simultaneous frequency divisions of
2, 4 and 8 are available at the Q1, Q2
and Q3 outputs. Independent use of
the first flip-flop is available if the reset
function coincides with reset of the
3-bit ripple-through counter.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF; VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay CP0 to Q0
CL = 15 pF; VCC =5 V
12
15
ns
fmax
maximum clock frequency
100
77
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per package
notes 1 and 2
22
pF
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