參數(shù)資料
型號(hào): 74LCX07
廠商: 意法半導(dǎo)體
英文描述: LOW VOLTAGE CMOS HEX BUFFER (OPEN DRAIN) WITH 5V TOLERANT INPUTS
中文描述: 低電壓CMOS六角緩沖區(qū)(開漏)與5V容限輸入
文件頁(yè)數(shù): 1/11頁(yè)
文件大小: 193K
代理商: 74LCX07
1/11
September 2004
I
5V TOLERANT INPUTS
HIGH SPEED:
t
PD
= 5.2ns (MAX.) at V
CC
= 3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
PCI BUS LEVELS GUARANTEED AT 24 mA
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 07
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
I
I
I
I
I
I
I
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DESCRIPTION
The 74LCX07 is a low voltage CMOS OPEN
DRAIN HEX BUFFER fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and high
speed 3.3V applications. It can be interfaced to 5V
signal environment for inputs.
The internal circuit is composed of 2 stages
including buffer output, which provides high noise
immunity and stable output.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LCX07
LOW VOLTAGE CMOS HEX BUFFER (OPEN DRAIN)
WITH 5V TOLERANT INPUTS
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE
T & R
SOP
TSSOP
74LCX07MTR
74LCX07TTR
TSSOP
SOP
Rev. 4
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