參數(shù)資料
型號(hào): 74LCX112SJX
廠商: Fairchild Semiconductor
文件頁(yè)數(shù): 4/9頁(yè)
文件大?。?/td> 0K
描述: IC FLIP FLOP DUAL JK NEG 16SOP
標(biāo)準(zhǔn)包裝: 2,000
系列: 74LCX
功能: 設(shè)置(預(yù)設(shè))和復(fù)位
類型: JK 型
輸出類型: 差分
元件數(shù): 2
每個(gè)元件的位元數(shù): 1
頻率 - 時(shí)鐘: 150MHz
延遲時(shí)間 - 傳輸: 7ns
觸發(fā)器類型: 負(fù)邊沿
輸出電流高,低: 24mA,24mA
電源電壓: 2 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
www.fairchildsemi.com
4
74LCX1
12
AC Electrical Characteristics
Note 4: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Capacitance
Symbol
Parameters
TA = 40°C to 85°C, RL = 500
Units
VCC = 3.3V ± 0.3V
VCC = 2.7V
VCC = 2.5V ± 0.2V
CL=50 pF
CL = 50 pF
CL=30 pF
Min
Max
Min
Max
Min
Max
fMAX
Maximum Clock Frequency
150
MHz
tPHL
Propagation Delay
1.5
7.5
1.5
8.0
1.5
9.0
ns
tPLH
CPn to Qn or Qn
1.57.5
1.58.0
1.59.0
tPHL
Propagation Delay
1.5
7.0
1.5
8.0
1.5
8.4
ns
tPLH
CDn or SDn to Qn or Qn
1.57.0
1.78.0
1.58.4
tS
Setup Time
2.5
4.0
ns
tH
Hold Time
1.5
2.0
ns
tW
Pulse Width CP
3.3
4.0
ns
tW
Pulse Width (CD, SD)
3.3
4.0
ns
tREC
Recovery Time
2.0
2.5
4.5
ns
tOSHL
Output to Output Skew
1.0
ns
tOSLH
(Note 4)
1.0
Symbol
Parameter
Conditions
VCC
TA = 25°C
Units
(V)
Typical
VOLP
Quiet Output Dynamic Peak VOL
CL = 50 pF, VIH = 3.3V, VIL = 0V
3.3
0.8
V
CL = 30 pF, VIH = 2.5V, VIL = 0V
2.5
0.6
VOLV
Quiet Output Dynamic Valley VOL
CL = 50 pF, VIH = 3.3V, VIL = 0V
3.3
0.8
V
CL = 30 pF, VIH = 2.5V, VIL = 0V
2.5
0.6
Symbol
Parameter
Conditions
Typical
Units
CIN
Input Capacitance
VCC = Open, VI = 0V or VCC
7pF
COUT
Output Capacitance
VCC = 3.3V, VI = 0V or VCC
8pF
CPD
Power Dissipation Capacitance
VCC = 3.3V, VI = 0V or VCC, f = 10 MHz
25
pF
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