參數(shù)資料
型號： 74LCX139TTR
廠商： 意法半導(dǎo)體
英文描述： LOW VOLTAGE CMOS DUAL 2 TO 4 DECODER/DEMULTIPLEXER
中文描述： 低電壓CMOS雙2日至4譯碼器/解復(fù)用器
文件頁數(shù)： 1/12頁
文件大?。?/td> 279K
代理商： 74LCX139TTR
1/12
September 2004
I
5V TOLERANT INPUTS
HIGH SPEED:
t
PD
= 6.2ns (MAX.) at V
CC
= 3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 139
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
I
I
I
I
I
I
I
I
I
DESCRIPTION
The 74LCX139 is a low voltage CMOS DUAL 2
TO
4
LINE
DECODER/DEMULTIPLEXER
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
It is ideal for low power and high speed 3.3V
applications; it can be interfaced to 5V signal
environment for inputs.
The active low enable input can be used for gating
or as a data input for demultiplexing applications.
While the enable input is held high, all four outputs
are high independently of the other inputs.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LCX139
LOW VOLTAGE CMOS
DUAL 2 TO 4 DECODER/DEMULTIPLEXER
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE
T & R
SOP
TSSOP
74LCX139MTR
74LCX139TTR
TSSOP
SOP
Rev. 3
相關(guān)PDF資料
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