參數(shù)資料
型號: 74LCX16240
廠商: 意法半導體
英文描述: Low Voltage CMOS 16-Bit Buffer (3-State INV.) with 5V Tolerant Inputs and Outputs(低壓CMOS總線緩沖器)
中文描述: 低電壓的CMOS 16位緩沖器(三態(tài)刑事調查。與5V容限輸入和輸出(低壓的CMOS總線緩沖器))
文件頁數(shù): 5/8頁
文件大小: 80K
代理商: 74LCX16240
TEST CIRCUIT
TEST
SWITCH
Open
6V
GND
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
, t
PHZ
C
L
=50 pFor equivalent (includes jigand probe capacitance)
R
L
=R
1
=500
or equivalent
R
T
=Z
OUT
of pulse generator (typically50
)
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
T
A
= 25
o
C
Min.
Typ.
Unit
V
CC
(V)
Max.
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance (note 1)
3.3
3.3
3.3
V
IN
=0toV
CC
V
IN
=0toV
CC
f
IN
=10MHz
V
IN
=0or V
CC
7
15
60
pF
pF
pF
1) C
PD
isdefined as the value ofthe IC’s internalequivalent capacitance which iscalculated fromtheoperating currentconsumption without load. Average
operting current can beobtained bythe followingequation. I
CC
(opr) = C
PD
V
CC
f
IN
+I
CC
/n(per circuit)
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
= 2.5 ns)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
Waveform
-40 to 85
o
C
Min.
1.5
1.5
1.5
1.5
1.5
1.5
Max.
5.3
4.5
6.0
5.4
5.4
5.3
1.0
t
PLH
t
PHL
Propagation Delay Time
2.7
1
ns
3.0to3.6
2.7
3.0to3.6
2.7
3.0to3.6
3.0to3.6
t
PZL
t
PZH
Output Enable Time
2
ns
t
PLZ
t
PHZ
Output Disable Time
2
ns
t
OSLZ
t
OSHL
Output to Output Skew Time (note 1, 2)
ns
1) Skew isdefined as the absolute value of the difference between theactual propagation delay forany twooutputs ofthe samedevice switching in the
same direction, either HIGHor LOW (t
OSLH
=|t
PLHm
-t
PLHn
|,t
OSHL
=|t
PHLm
-t
pHLn
|)
2) Parameter guaranteed bydesign
74LCX16240
5/8
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74LCX16244 Low Voltage CMOS 16-Bit Buffer (3-State) with 5V Tolerant Inputs and Outputs(三態(tài)低電壓16位緩沖器)
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